Semiconductor device with modified channel compressive stress

Details Semiconductor device with modified channel compressive stress Semiconductor device with modified channel compressive stress

2005-12-13

2005-12-13

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S411000, C257S412000

Reexamination Certificate

active

06975006

ABSTRACT:
A semiconductor device includes a substrate and a gate region on top of a substrate. First and second gate sidewall liners are situated on first and second sides of the gate region respectively, the first and second sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. First and second recessed spacers are situated on top of the first and second sidewall liners respectively. The height of the first and second spacers is lower than the height of the gate sidewall liner whereas the width of the horizontal part of the sidewall liner is shorter than the width of the spacer.

REFERENCES:
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patent: 6013569 (2000-01-01), Lur et al.
patent: 6512266 (2003-01-01), Deshpande et al.
patent: 6521964 (2003-02-01), Jan et al.
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patent: 6746927 (2004-06-01), Kammler et al.
Ootsuka, F., et al., “A High Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Applications”, IDEM 00, IEEE 0-7803-6438, (Apr. 2000), pp. 575-578.
Tiwari, S., et al. “Hole Mobility Improvement in Silicon-on-Insulator and Bulk Silicon Transistors Using Local Strain”, IDEM 97, (Apr. 2000), pp. 939-941.

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