Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-09
2003-12-02
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06657247
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same, and more specifically, to a structure of a metal insulator metal (hereinafter referred to as MIM) capacitance element and a method of producing the same.
2. Description of the Background Art
In recent years, in an analog circuit, there is an increasing demand for a large capacity capacitance element with high accuracy. Conventionally, a gate capacitance element and a PIP (Poly Si Insulator Poly Si) capacitance element have been mounted on the analog circuit as the capacitance elements. The structures of these capacitance elements, however, involve problems such as high resistance of an electrode and voltage dependency of a capacitance value due to a change in a thickness of a depletion layer so that they are not suitable for high accuracy capacitance elements. Moreover, when compared to a manufacturing step of a semiconductor device that does not include a PIP capacitance element, the manufacturing step of a semiconductor device with the PIP capacitance element additionally requires a heat treatment step so that the characteristics of a high accuracy transistor and a resistance element are affected, which makes it difficult to control the manufacturing step while taking these characteristics into account.
On the other hand, the MIM capacitance elements disclosed in Japanese Patent Laying-Open Nos. 2000-228497 and 2000-101023 and U.S. Pat. No. 5,926,359 have an upper layer electrode and a lower layer electrode forming a metal structure so that they offer the advantages of lower resistance in the electrode, of no voltage dependency of the capacitance value by a depletion layer, and of not requiring extra heat treatment during the formation of the MIM structure, and so on. Thus, in the analog circuit, the MIM capacitance element is gradually replacing the PIP capacitance element.
In a case where the MIM capacitance element is used in an analog circuit, however, there is a need further to optimize the structure and the manufacturing steps with respect to high reliability (lifetime) of the MIM capacitance element.
SUMMARY OF THE INVENTION
The object of the present invention is to make possible high reliability (lifetime) of an MIM capacitance element in a semiconductor device using the MIM capacitance element by improving the structure of the MIM capacitance element as well as its manufacturing steps.
In order to achieve the above object, according to one aspect of the semiconductor device based on the present invention, the semiconductor device includes a capacitance element formed by stacking a lower metal layer, a dielectric layer, and an upper metal layer; an interconnection layer provided in a prescribed region; a first interconnection line connecting via a first via hole to the lower metal layer; a second interconnection line connecting via a second via hole to the upper metal layer; and a third interconnection line connecting via a third via hole to the interconnection layer, wherein the lower metal layer is made of the same material formed in the same manufacturing step as that of the interconnection layer, and the first interconnection line and the second interconnection line are made of the same material formed in the same manufacturing step as that of the third interconnection line after the first via hole, the second via hole, and the third via hole are formed at the same time.
According to the above-described semiconductor device, since the lower metal layer forming the capacitance element is formed at the same time in the step of manufacturing the interconnection layer, only a step that utilizes one sheet of mask (photolithography step) needs to be added for separating a conductive layer into an interconnection layer and a lower metal layer so that there is no need to provide a separate step for forming the lower metal layer.
In addition, a step of forming the first via hole that passes through the lower metal layer and the second via hole that passes through the upper metal layer takes place at the same time as the conventional step of forming the third via hole that passes through an interconnection layer, and the step of forming the first and second interconnection lines respectively within the first and second via holes takes place at the same time as the step of forming the third interconnection line within the third via hole, so that the present structure can be obtained with ease.
Moreover, according to this invention, a thickness of the upper metal layer is preferably made to be thinner than a thickness of the lower metal layer. Thus, it becomes possible to facilitate the planarization by a CMP (Chemical Mechanical Polishing) technique of a surface of an interlayer insulating film formed on the capacitance element.
In addition, according to this invention, the dielectric layer and the upper metal layer are preferably patterned using the same mask so that they have the same shape.
In addition, according to this invention, the upper metal layer preferably has a first metal layer provided on the dielectric layer and a second metal layer provided on the first metal layer, and an end surface of the first metal layer recedes inwardly from an end surface of the second metal layer. According to this arrangement, the end surface of the first metal layer of the upper metal layer forming the capacitance element is not directly exposed to an etchant utilized during the removal of the dielectric layer so that damage is alleviated in the end portion of the first metal layer, and thus it becomes possible to improve the reliability of the capacitance element due to reduction in the leak in the capacitance element.
Moreover, according to this invention, the end surface of the upper metal layer is preferably covered with a sidewall insulating film. According to this structure, since at least a side surface of the upper metal layer is covered by the sidewall insulating film, it becomes possible to prevent the leak between the lower metal layer and the upper metal layer even when an anti-reflection film or the like is formed on the upper metal layer.
In addition, in order to achieve the above-description object, according to another aspect of the semiconductor device based on the present invention, an arrangement of the semiconductor device is characterized in that a lower interconnection layer is provided below the semiconductor device with an interlayer insulating film disposed therebetween, and that in a region below the upper metal layer forming the capacitance element, no via hole exists in the interlayer insulating film between the lower metal layer and the lower interconnection layer. With this arrangement, the unevenness of the surface of the dielectric layer would no longer be created so that a surface area of the dielectric layer would take a value as designed, and the capacitance of the capacitance element can be stabilized.
Moreover, in order to achieve the above-described object, according to a further aspect of the semiconductor device based on the present invention, an arrangement of the semiconductor device is characterized in that an interlayer insulating film is provided below the semiconductor device, and that no interconnection layer exists in the interlayer insulating film in a region below the upper metal layer forming the capacitance element. With this arrangement, the parasitic capacitance that occurs between interconnection layers can be reduced, and the reliability of the function of the semiconductor device having the capacitance element can be improved.
Moreover, in order to achieve the above-described object, according to a still further aspect of the semiconductor device based on the present invention, an arrangement of the semiconductor device has a first interlayer insulating film provided below the semiconductor device, a second interlayer insulating film provided below the first interlayer insulating film, and a metal interconnection layer provided in a region below the second interlayer insulating fil
Morita Kiyoaki
Yoshiyama Kenji
Fahmy Wael
McDermott & Will & Emery
Pham Hoai
LandOfFree
Semiconductor device with MIM capacitance element does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with MIM capacitance element, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with MIM capacitance element will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3159944