Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – With inversion-preventing shield electrode
Reexamination Certificate
2000-02-03
2002-06-11
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
With inversion-preventing shield electrode
C257S620000
Reexamination Certificate
active
06404040
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device formed with the use of the peripheral areas (in particular, scribing line areas) of element forming areas, and also to a manufacturing method of such a semiconductor device.
2. Description of Related Art
When forming semiconductor chips on a wafer, there are formed, around the chips, areas where no elements are formed. These areas serve as allowances to be cut when the chips are cut from the wafer, and are called scribing lines.
Conventionally, such scribing lines are utilized merely as chip cutting allowances.
On the other hand, for disposing bump electrodes or bonding electrodes on a chip, it is required to dispose the electrodes so as to prevent the wirings among the electrodes from getting complicated. This lowers the degree of freedom for the arrangement of the electrodes. This disadvantageously imposes restrictions on the miniaturization and high integration of chips.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide semiconductor device formed with the use of the peripheral areas around element forming areas.
More specifically, it is an object of the present invention to provide a semiconductor device formed with the scribing line areas utilized for disposing electrodes or wirings, thus not only facilitating the connection among the electrodes on the semiconductor elements, but also improving the degree of freedom for wiring.
It is another object of the present invention to provide a method of manufacturing a semiconductor device with the use of the peripheral areas around element forming areas.
It is a further object of the present invention to provide a semiconductor device having a chip-on-chip structure in which there are piled up, on each other, semiconductor elements each formed with the use of the peripheral areas around element forming areas.
A semiconductor device according to the present invention comprises: a semiconductor substrate; an element forming area provided on the semiconductor substrate; a peripheral area surrounding, on the semiconductor substrate, the element forming area; and a metal layer formed at the peripheral area.
According to the arrangement above-mentioned, when the metal layer is for example connected to a predetermined electrode of the semiconductor substrate, this metal layer can be utilized as an electrode or a wiring.
For example, the metal layer may be connected to the grounding potential. This arrangement produces a shielding effect. Further, when this metal layer is utilized as the grounding line, an electrode inside of the element forming area can readily be grounded.
The metal layer may be connected to the power potential. According to this arrangement, the power can readily be fed to an electrode inside of the element forming area. In this case, too, the shielding effect is obtained.
The metal layer may be formed as surrounding the whole periphery of the element forming area. This produces an excellent shielding effect.
The metal layer may be divided into at least two portions. In this case, the divided portions can be utilized as electrodes or wirings different in potential from each other.
The peripheral area may be a scribing line area.
The metal layer may be a bump (projecting electrode). The bump has characteristics of low resistance and high thermal conductivity. In view of these characteristics, when the bump is connected to a predetermined electrode on the semiconductor element, this bump can more suitably be utilized as an electrode.
The metal layer may be formed simultaneously with the formation of a surface electrode (e.g., bump) within the element forming area at a step of forming this surface electrode. This enables the metal layer to be formed with no addition of a special step.
A diffusion layer is preferably formed on the semiconductor substrate immediately below the metal layer. More specifically, the diffusion layer may be formed for example at the scribing line area, and the bump may be formed on the diffusion layer. Dependent on the conduction types of both the diffusion layer and the semiconductor substrate, there is assured either ohmic contact with the semiconductor substrate, or insulation therefrom.
The metal layer may be formed in the scribing line area at other area than the cutting area. This makes it easier to cut a large semiconductor substrate (wafer) into individual semiconductor elements.
The metal layer may be connected, through a connection metal layer, to a surface electrode formed within the element forming area. This connection metal layer may simultaneously be formed at the time when the surface electrode (e.g., bump) is formed. When the connection metal layer is formed in the form of a bump, a large electric current can advantageously flow.
Preferably, the semiconductor device of the present invention further comprises a lateral-wall metal layer which covers the lateral walls of the semiconductor substrate. This lateral-wall metal layer is preferably connected to the metal layer formed at the peripheral area. In this case, when the metal layer at the peripheral area is utilized as the grounding line or the power line, the lateral sides of the semiconductor element can also be shielded.
Preferably, the semiconductor device of the present invention further comprises a back-face metal layer which covers the back face of the semiconductor substrate. This makes it possible to expect a further improvement in shielding effect.
A semiconductor device manufacturing method of the present invention comprises: a step of providing a plurality of element forming areas on a semiconductor substrate; a step of forming a metal layer at scribing line areas between adjacent element forming areas; and a step of cutting the semiconductor substrate along the cutting areas in the scribing line areas.
The metal-layer forming step may be arranged such that the metal layer is formed at other areas of the scribing line areas than the cutting areas.
Preferably, the metal-layer forming step is conducted simultaneously with a step of forming surface electrodes within the element forming areas.
These and other features, objects and advantages of the present invention will be more fully apparent from the following detailed description set forth below when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5739546 (1998-04-01), Saitou et al.
patent: 5834829 (1998-11-01), Dinkel et al.
Hikita Junichi
Kumamoto Nobuhisa
Nakagawa Yoshikazu
Potter Roy
Rader & Fishman & Grauer, PLLC
Rohm Co. Ltd
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