Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-28
2002-10-15
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S297000
Reexamination Certificate
active
06465829
ABSTRACT:
This application is based on Japanese Patent Application 2000-155586, filed on May 26, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of basic units each containing a memory cell and a logic cell on the same semiconductor substrate.
b) Description of the Related Art
A content addressable memory (CAM) has become noteworthy in order to realize high sophistication and high speed of an information processing system. CAM has the function that a logic cell can detect a match between the contents stored in a memory cell and externally supplied data. The memory cell is generally made of an SRAM.
Gillingham has proposed a CAM having the structure that the memory cell is made of a dynamic random access memory (DRAM). With this structure, a memory cell of the basic unit can be made of two access transistors, two capacitors, and four search/compare transistors (for a ternary CAM). However, the most efficient structure of CAM and its manufacture techniques are not still established.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor device having a plurality of basic units each containing a memory cell and a logic cell on the same semiconductor substrate, the device being easy to be manufactured with high integration.
Another object of the invention is to provide a semiconductor device capable of realizing a high performance CAM.
According to one aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate and a plurality of basic units formed on the semiconductor substrate each having a memory element and a logic element and a same plan layout or a bilateral symmetry layout, the basic unit comprising: an isolation insulating region formed on a surface of the semiconductor substrate for defining first and second active regions; a transfer transistor having a first gate electrode formed traversing the first active region and a pair of first source/drain regions formed on both sides of the first gate electrode in the first active region; a word line connected to the first gate electrode; a bit line connected to one of the pair of first source/drain regions; serially connected transistors having second and third gate electrodes formed traversing the second active region, a connection node formed between the second and third gate electrodes in the second active region, a pair of second source/drain regions formed outside the second and third gate electrodes, and a suicide electrode formed on the connection node and on the pair of second source/drain regions; a first signal line connected to the silicide electrode on one of the pair of second source/drain regions; a second signal line connected to the silicide electrode on the other of the pair of second source/drain regions; a third signal line connected to the second gate electrode; a storage electrode formed in an area above the other of the pair of first source/drain regions and at least a portion of the third gate electrode; a capacitor dielectric film formed on a surface of the storage electrode; a first conductive connection member formed on and under the storage electrode for connecting the storage electrode to the other of the pair of first source/drain regions; and a second conductive connection member formed on and under the storage electrode for connecting the storage electrode to the third gate electrode.
A semiconductor device with an efficient structure can be provided having a plurality of basic units each having a memory element and a logic element.
An integration degree of CAM can be improved and the manufacture processes can be stabilized.
REFERENCES:
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patent: 5146300 (1992-09-01), Hamamoto et al.
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patent: 5993363 (1999-11-01), Shindo
patent: 6320777 (2001-11-01), Lines et al.
patent: 3-166761 (1991-07-01), None
patent: WO 00/60604 (2000-10-01), None
Lines et al.: “66 MHZ 2.3 M. Ternary Dynamic Content Addressable Memory”, IEEE Int. Workshop on Memory Technology, Design and Testing, Aug. 7-8, 2000; pp. 101-105.
Ema Taiji
Takeda Shigetoshi
Armstrong Westerman & Hattori, LLP
Wilson Allan R.
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