Semiconductor device with increased effective channel length...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S344000

Reexamination Certificate

active

10845688

ABSTRACT:
A semiconductor device with an increased effective channel length and a method of manufacturing the same. The device includes a semiconductor substrate, a gate insulating layer disposed on the semiconductor substrate, a gate electrode structure disposed on a predetermined portion of the gate insulating layer, an insulating layer for preventing short channel disposed on the surface of the resultant structure where the gate electrode structure is disposed, and a source region and a drain region disposed in the semiconductor substrate on either side of the gate electrode structure. Both the source region and the drain region are spaced apart from the gate electrode structure by the thickness of the insulating layer. The channel length of a MOS transistor can be thereby increased.

REFERENCES:
patent: 4951100 (1990-08-01), Parrillo
patent: 5491099 (1996-02-01), Hsu
patent: 5847428 (1998-12-01), Fulford et al.
patent: 5874343 (1999-02-01), Fulford et al.
patent: 6551870 (2003-04-01), Ling et al.
patent: 1020010002286 (2001-01-01), None
patent: 010015244 (2001-02-01), None
patent: 1020010059856 (2001-07-01), None
English language abstract of Korean Publication No. 010015244.
English language abstract of Korean Publication No. 1020010059856.
English language abstract of Korean Publication No. 1020010002286.
Hamamoto, et al. “On the Retention Time Distribution of Dynamic Random Access Memory (DRAM)” IEEE transactions on electron devices, vol. 45, No. 6, Jun. 1998. pp. 1300-1309.

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