Semiconductor device with incorporated stress reducing means

Details Semiconductor device with incorporated stress reducing means Semiconductor device with incorporated stress reducing means

1991-05-07

1993-07-27

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With stress relief

257666, 257673, 257787, H01L 2328

Patent

active

052313034

ABSTRACT:
A semiconductor device comprises a semiconductor chip mounted within a prepared aperture formed in a flexible film carrier. A conductive lead pattern is formed on the surface of the film carrier and the inner lead ends of the lead pattern project over and into the film aperture in aligned relation with a plurality of bonding pads formed on the active surface of the semiconductor chip. The semiconductor chip, or the semiconductor chip together with inner portions of the conductive lead pattern, are encapsulated with a sealing resin to the film carrier. A spatial interval, A defined by the edge of the carrier aperture and the edge of the outer side periphery of the semiconductor chip to be installed in the device aperture, is set within the range of about 0.4 mm to 0.8 mm. Also, the inner leads are provide with a small extended length, preferably in those portions extending into and over the device aperture. Further, slack lead portions or flexible carrier support members may be provided for the inner leads to absorb stresses occurring from transport and handling of the semiconductor device after connection of the inner lead ends with the semiconductor chip bonding pads as well as stresses occurring due to thermal resin sealing and setting during the step of device resin encapsulation.

REFERENCES:
patent: 4736236 (1988-04-01), Butt
patent: 4743956 (1988-05-01), Olla et al.
patent: 5031022 (1991-07-01), Yamamoto et al.

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