Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-11
2004-09-28
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S356000, C257S357000, C257S173000
Reexamination Certificate
active
06798022
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a metal-oxide-semiconductor field-effect transistor with improved protection against electrostatic discharge.
2. Description of the Related Art
The shrinking dimensions of complementary metal-oxide-semiconductor (CMOS) integrated circuits require special designs for transistors that conduct large amounts of current. Such transistors are found in particular in CMOS input and output circuits, where they are needed to drive heavy loads and to provide protection from electrostatic discharge (ESD).
One known high-current transistor design is the finger design illustrated in
FIG. 1
, which places multiple gate electrodes
1
between an alternating series of source
3
and drain
5
diffusions. If the transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor, for example, the source and drain diffusions
3
,
5
are n-type diffusions disposed in a p-type well or substrate
7
, and the transistor is surrounded by a p
+
-type diffusion
9
through which a fixed potential is supplied to the well or substrate
7
. Since the p
+
-type diffusion
9
helps prevent CMOS latch-up, it is also known as a guard ring. For an n-channel transistor, the source and guard ring diffusions
3
,
9
are normally coupled to ground. The finger design provides ample total channel width to drive a large load, or to shunt ESD current safely from the drain diffusions
5
to the source diffusions
3
.
As shown in
FIG. 2
, however, parasitic diodes
10
are formed between the ends of the drain diffusions
5
and the guard ring diffusion
9
. If these diffusions
5
,
9
are too close together, the parasitic diodes
10
may break down under ESD stress, leading to thermal damage as discharge current surges through the relatively small total diode width. To avoid such damage, enough space to prevent breakdown must be provided between the drain diffusions
5
and guard ring diffusion
9
, but this increases the area of the transistor.
U.S. Pat. No. 5,714,784, issued to Ker et al., discloses an alternative design, shown in
FIG. 3
, in which a guard ring diffusion
9
, source diffusion
11
, and gate electrode
13
form concentric square loops converging on a central square drain diffusion
15
. By separating the drain and guard ring diffusions, this design eliminates the parasitic diode shown in
FIG. 2
, enabling the transistor dimensions to be reduced without loss of ESD robustness.
The transistor in
FIG. 3
is vulnerable to damage, however, at the overlapping corners
16
of the gate electrode
13
and drain diffusion
15
. This problem is thought to result from electric field concentration combined with poor gate oxide quality at the corners
16
. Although the failure mechanism is not understood in detail, it is known that in general the gate-drain breakdown voltage of a field-effect transistor decreases as the number of corners in its active region increases. The result of an oxide breakdown under ESD stress is often fatal to the device: the ESD current burns a hole through the oxide film.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device with improved protection from electrostatic discharge.
Another object of the invention is to simplify the design of a semiconductor device to provide a specified level of protection from electrostatic discharge.
The inventive semiconductor device has a semiconductor substrate covered by an oxide film.
According to a first aspect of the invention, a polygonal drain diffusion is disposed in the substrate, an annular polygonal source diffusion is disposed in the substrate surrounding the drain diffusion, and a plurality of gate electrodes are disposed on the oxide film between mutually facing sides of the polygonal source and drain diffusions, partially overlapping the facing sides of the source and drain diffusions but avoiding corners of the drain diffusion.
According to a second aspect of the invention, an annular polygonal gate electrode is disposed on the oxide film, a plurality of source diffusions are disposed in the substrate, facing and partially beneath respective exterior sides of the gate electrode, and a polygonal drain diffusion with deleted corners is disposed in the substrate, facing and partially beneath the interior sides of the gate electrode but avoiding the interior corners of the gate electrode.
According to a third aspect of the invention, a plurality of drain diffusions are disposed in the substrate on respective sides of a polygonal area of the substrate, avoiding corners of the polygonal area. A plurality of source diffusions are disposed in the substrate exterior to the polygonal area and drain diffusions, facing the drain diffusions at a certain distance. A plurality of gate electrodes are disposed on the oxide film between mutually facing sides of the source and drain diffusions, partially overlapping the facing sides of the source and drain diffusions.
In any of these aspects of the invention, the semiconductor device may also include an annular guard ring diffusion disposed in the substrate surrounding the source diffusion or diffusions. The semiconductor substrate and guard ring diffusion are preferably of a first conductive type, the source and drain diffusions being of a second conductive type.
The semiconductor device may have a first metal interconnection pattern coupling the source diffusion or diffusions to a power-supply or ground potential, and a second metal interconnection pattern coupling the drain diffusion or diffusions to an input or output lead of an integrated circuit in which the semiconductor device is a circuit element. The first metal interconnection pattern may also couple the gate electrode or electrodes to the power-supply or ground potential.
The invention provides improved protection from electrostatic discharge by avoiding gate-drain overlap in corner areas, thereby avoiding electric field concentration in areas where oxide quality is comparatively poor.
The second and third aspects of the invention simplify the design of the semiconductor device because the level of protection from electrostatic discharge depends linearly on the polygonal side dimensions of the device.
The third aspect of the invention also simplifies the design of the semiconductor device by providing added layout flexibility.
REFERENCES:
patent: 5119162 (1992-06-01), Todd et al.
patent: 5714784 (1998-02-01), Ker et al.
patent: 5838050 (1998-11-01), Ker et al.
patent: 6097066 (2000-08-01), Lee et al.
patent: 6621133 (2003-09-01), Chen et al.
patent: 6680512 (2004-01-01), Nishikawa et al.
Kuroda Toshikazu
Sasaki Katsuhito
Forde Remmon R.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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