Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-18
2002-12-03
Eckert, II, George C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S394000, C257S401000, C438S298000
Reexamination Certificate
active
06489657
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a high withstand or threshold voltage MOS (metal oxide semiconductor) transistor and a method of producing the same.
More particularly, the present invention relates to a semiconductor device comprising a high withstand voltage MOS transistor having an offset drain/offset source structure that includes a channel region and a parasitic channel stopper layer formed below a field insulating film that abuts the channel region. The channel stopper layer has an impurity concentration gradient that decreases in the direction of the channel region, to substantially prevent a high electric field from being generated between the channel region and the parasitic channel stopper when the transistor is in an operational state.
2. Description of the Related Art
Along with the increase in size of displays of personal computers and television sets for home use, the market for displays has expanded rapidly. Also, in the current field of displays, while CRTs having a high definition, a high luminance, a wide viewing angle, a high contrast, and other superior view ability are most widespread, attention is focusing on the increase in the space they occupy along with their future enlargement. In addition to liquid crystal displays and projector displays, plasma displays of a new type using plasma and other flat panel displays capable of being made thinner have been looked to as the next-generation of displays to take the place of CRTs. In view of this situation, in the field of semiconductor devices , a high withstand voltage process able to form a driver IC of a high withstand voltage of several hundred volts for controlling plasma has been required.
For facilitating understanding of the present invention, a conventional high withstand voltage NMOS transistor and high withstand voltage PMOS transistor will be explained with reference to the drawings.
FIG. 1
is a top view of a conventional high withstand voltage NMOS transistor viewed from an upper side of the substrate.
FIG. 2A
is a cross-sectional view along X-X′ of FIG.
1
.
FIG. 2B
is a cross-sectional view along Y-Y′ of FIG.
1
.
FIG. 3
is a top view of a conventional high withstand voltage PMOS transistor viewed from an upper side of the substrate.
FIG. 4A
is a cross-sectional view along X-X′ of FIG.
3
.
FIG. 4B
is a cross-sectional view along Y-Y′ of FIG.
3
. In the top views of FIG.
1
and
FIG. 3
, a broken line represents a part that is overlapped with another part represented by a solid line.
These high withstand voltage MOS transistors are called LOD/S (LOCOS offset drain/source)-type LDMOS transistors. The structure of the NMOS transistor shown in
FIGS. 1
,
2
A and
2
B will now be explained. A buried layer doped with a p-type impurity (PBL)
3
is formed in a predetermined region of a p-type silicon semiconductor substrate
1
on which an n-type epitaxial layer
5
is then formed. A p-well
8
and n-wells
9
are formed in a surface part of the n-type epitaxial layer
5
.
Also, on the p-well
8
of a region separated by a field insulating film, that is, LOCOS oxide film
10
, a gate electrode
14
is formed with side wall protection oxide films
17
adjacent a gate oxide film
12
. On the gate electrode
14
, as shown in
FIG. 2B
, a gate electrode plug
14
a
is formed. On the surface of the n-wells
9
separated from each other by the p-well
8
, an n-type source region
18
n
and an n-type drain region
19
n
are formed. These are connected to a source electrode
20
and a drain electrode
21
respectively.
As shown in
FIG. 2B
, an n-channel formation region
22
is formed on a surface of the p-well
8
just below the polycrystalline silicon gate electrode
14
. When voltage is supplied on the gate electrode
14
, a channel is formed in the n-channel region
22
. Also, at parts of the p-well
8
contacting the LOCOS oxide film
10
, parasitic n-channel stopper layers
11
containing a p-type impurity are formed so as to sandwich this n-channel formation region
22
between them. Due to this, the withstand voltage is increased.
Further, as shown in
FIGS. 2A and 2B
, in the above transistor, silicon oxide films
15
,
16
covering the upper side are formed.
The PMOS transistor shown in FIG.
3
and
FIGS. 4A and 4B
has a similar structure. An n-well
9
is formed on a n-type buried layer
4
formed on the substrate
1
. Also, on the surface of the p-well
8
separated by the n-well
9
, a p-type source region
18
p
and a p-type drain region
19
p
are formed. A p-channel formation region
23
is formed on a surface of the n-well
9
just below the polycrystalline silicon gate electrode
14
. Also, at parts of the n-well
9
contacting the LOCOS oxide film
10
, parasitic p-channel stopper layers
13
containing an n-type impurity are formed so as to sandwich the p-channel formation region
23
between them. Due to this, the withstand voltage is increased.
These high withstand voltage NMOS and PMOS transistors are called LOD/S (LOCOS offset drain/source)-type LDMOS transistors. In these MOS transistors, for the purpose of securing a high BVds Ounction withstand voltage between source and drain), for example in the case of the NMOS, as shown in
FIG. 2A
, the n-type source region
18
and n-type drain region
19
are formed away from the p-well
8
by the LOCOS oxide film
10
.
In this MOS transistor, when a reverse bias is supplied between the source and the drain, a depletion layer extends from a junction of the p-well
8
of a low concentration of impurity and the n-well
9
to the n-well
9
. The withstand voltage is secured by using the extension of the depletion layer to the n-well
9
for easing the electric field.
In addition, in this transistor, the withstand voltage is increased further by employing a RESURF (reduced surface field) technique, that is, easing of the electric field at the surface of the n-well
9
using an extension of a depletion layer at the junction of the p-type silicon semiconductor substrate
1
of a low concentration of impurity and the n-type epitaxial layer
5
of a low concentration of impurity in the surface direction.
Also, unlike general LOD-type LDMOS transistors, since these MOS transistors have a symmetrical structure right and left from the gate, that is, in the direction of the source and the drain, it is possible to obtain a high withstand voltage not only between a backgate connected generally to a reference voltage and the drain and between the gate and the drain or other drain sides but also between a backgate and the source and between the gate and source or other source sides.
However, when the NMOS transistor shown in
FIG. 2
is in an on state, that is, in the state where the source electrode
20
and drain electrode
21
have any voltage, a positive voltage is supplied on the polycrystalline silicon gate electrode
14
, a channel is formed in the n-channel formation region
22
as shown in
FIG. 2B
, and an electric current flows between the source and drain. When the source electrode
20
(or the drain electrode) voltage becomes a high voltage, a high electric field is generated at the junction of the n-channel region
22
and the parasitic n-channel stopper layer
11
(parts shown with arrows) and a junction breakdown is sometimes caused.
Further, it suffers from the disadvantage that carriers generated by this breakdown jump into the gate oxide film
12
due to the positive voltage supplied on the polycrystalline silicon gate electrode
14
, causing the threshold voltage V
th
to change.
Also, in the PMOS transistor too, as shown in
FIG. 4B
, when the voltage of the source electrode
20
becomes a high voltage, a high electric field is generated at the junction of the p-channel
23
and the parasitic p-channel stopper layer
13
(parts shown with arrows) and a breakdown is induced in the same manner. Then, it suffers from the disadvantage that carriers generated by this change the threshold voltage V
th
.
If an analo
Eckert II George C.
Sonnenschein Nath & Rosenthal
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