Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-19
2004-09-14
Kang, Donghee (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S300000, C257S306000, C257S908000, C438S238000, C438S239000, C438S386000, C438S399000
Reexamination Certificate
active
06791135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device integrating at least a memory circuit and at least an analogue circuit which includes an improved capacitive element, and a method of forming the same.
All of patents, patent applications, patent publications, scientific articles and the like, which will hereinafter be cited or identified in the present application, will, hereby, be incorporated by references in their entirety in order to describe more fully the state of the art, to which the present invention pertains.
2. Description of the Related Art
In recent years, a large number of a semiconductor device, which comprises a logic circuit hybridized with a memory circuit, have been designed for response to various purposes and applications. For example, a DRAM-hybrid logic circuit has been provided, wherein DRAM cells integrated into a logic circuit. Capacitive elements may, in case, be needed for not only a digital circuit which constitutes the DRAM cells but also an analogue circuit which constitutes the logic circuit. The capacitive element included in the analogue circuit for the logic circuit is formed in a separate process from another process for forming the other capacitive element included in the digital circuits for the DRAM cells. It may be possible that the capacitive element for the DRAM cell utilizes a polycrystalline silicon for at least one of paired top of bottom electrodes of the cell. This capacitive element having one or more polycrystalline silicon electrodes in the DRAM cell is not suitable as the capacitive element for the analogue circuit, in the light of capacitance value dependency upon applied voltage to the capacitive element.
The capacitive element varies in capacitance value, depending upon the variation of the applied voltage. This capacitance value dependency upon applied voltage may not be influential to the DRAM cell but may be influential to the analogue circuit. An ideal capacitive element in the analogue circuit is free of any substantial capacitance value dependency upon applied voltage.
For example, an MOS capacitor includes a part of a substrate and a gate electrode of a MOS transistor. Such MOS capacitor has a substantial capacitance value dependency upon applied voltage. For this reason, such the MOS transistor is unsuitable for the analogue circuit. Also, the capacitor constituting the DRAM cell has a substantial capacitance value dependency upon applied voltage. For this reason, such DRAM cell capacitor is also unsuitable for the analogue circuit. For those reasons, the process for forming the capacitor in the analogue circuit is separated from the process for forming the capacitor in the DRAM circuit.
FIG. 1
is a fragmentary cross sectional elevation view illustrative of a conventional structure of a semiconductor device including a DRAM region and an analogue circuit region in the prior art. The semiconductor device includes a DRAM region
1000
and an analogue circuit region
2000
over a silicon substrate
201
. The DRAM region
1000
includes a DRAM cell and its peripheral circuits.
Over the silicon substrate
201
, p-well regions
203
and n-well region
204
are selectively formed, so that the p-well regions
203
are isolated from each other by shallow trench isolations
202
. The p-well regions
203
are included in the DRAM region
1000
and the analogue circuit region
2000
, respectively. The p-well regions
203
are isolated from each other by the n-well region
204
.
Over the p-well regions
203
in the DRAM region
1000
and the analogue circuit region
2000
, a gate insulation film
205
is formed. Gate electrodes
206
are then formed on the gate insulation film
205
. Further, source and drain regions
207
are selectively formed in upper regions of the p-well regions
203
in the DRAM region
1000
and the analogue circuit region
2000
, whereby first and second transistors TR
11
and TR
12
are formed in the DRAM region
1000
and the analogue circuit region
2000
, respectively.
An inter-layer insulator
208
is then formed over the p-well regions
203
and the n-well region
204
, so that the inter-layer insulator
208
overlies the first and second transistors TR
11
and TR
12
. A planarization to a surface of the inter-layer insulator
208
is then made to form a planarized surface of the inter-layer insulator
208
.
A contact hole is formed in the inter-layer insulator
208
in the DRAM region
1000
. A contact plug
209
of polysilicon is formed in the contact plug. A silicon oxide film
210
is formed over the planarized surface of the inter-layer insulator
208
. A surface of the silicon oxide film
210
is then planarized. Cylinder-shaped holes
216
are formed in the silicon oxide film
210
, wherein the cylinder-shaped holes
216
are positioned in the DRAM region
1000
and the analogue circuit region
2000
. The cylinder-shaped holes
216
are much larger in diameter than the contact hole, within which the contact plug
209
has been formed. Conductive polysilicon films
211
with surface roughness are formed on bottom and side walls of the cylinder-shaped holes
216
. Silicon nitride films
212
are formed on rough surfaces of the conductive polysilicon films
211
, wherein the silicon nitride films
212
act as capacitive insulation films.
Conductive polysilicon films
213
are formed on the silicon nitride films
212
and on parts of the planarized surface of the silicon oxide film
210
, so that the conductive polysilicon films
213
completely fill the cylinder-shaped holes
216
and also extends over parts of the planarized surface of the silicon oxide film
210
, whereby a first capacitor C
11
is formed in the DRAM region
1000
. In the DRAM region
1000
, the conductive polysilicon film
213
acts as a top electrode of the first capacitor C
11
in the DRAM region
1000
. In the analogue circuit region
2000
, the conductive polysilicon film
213
acts as a bottom electrode of a second capacitor C
12
to be formed by further processes to be described below.
A capacitive insulation film
214
is selectively formed on a part of a top surface of the conductive polysilicon film
213
in the analogue circuit region
2000
. A top electrode
215
of tungsten silicide is selectively formed on the capacitive insulation film
214
, whereby the second capacitor C
12
is formed in the analogue circuit region
2000
.
An inter-layer insulator
217
is formed over the first and second capacitors C
11
and C
12
. A surface of the inter-layer insulator
217
is then planarized. Contact holes are formed in the inter-layer insulator
217
, so that the contact holes communicate with the top electrode
213
of the first capacitor C
11
, the top and bottom electrodes
215
and
213
of the second capacitor C
12
. Contact plugs
218
are then formed on the contact holes, so that the contact plugs
218
are connected with the top electrode
213
of the first capacitor C
11
, and the top and bottom electrodes
215
and
213
of the second capacitor C
12
. Interconnections
219
are formed on the planarized surface of the inter-layer insulator
217
, wherein the interconnections
219
are connected with the contact plugs
218
. The interconnections
219
are electrically connected through the contact plugs
218
to the top electrode
213
of the first capacitor C
11
, and the top and bottom electrodes
215
and
213
of the second capacitor C
12
.
In the analogue circuit region
2000
, the second capacitor C
12
has the bottom electrode
213
of the conductive polysilicon and the top electrode
215
of tungsten silicide. In the DRAM region
1000
, the first capacitor C
11
has. the top and bottom electrodes
213
and
211
, both of which are made of polysilicon. The above materials for the top and bottom electrodes
215
and
213
of the second capacitor C
12
are effective to reduce the capacitance dependency upon applied voltage.
As described above, the second capacitor C
Kang Donghee
NEC Electronics Corporation
Young & Thompson
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