Semiconductor device with high speed latch operation

Details Semiconductor device with high speed latch operation Semiconductor device with high speed latch operation

2002-03-19

2004-03-30

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S230060, C365S230080

Reexamination Certificate

active

06714438

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device provided with an input latch that captures a signal in synchronization with a clock signal.
2. Description of the Related Art
As the operation speed of CPUs increases, semiconductor devices such as semiconductor memory devices associated with the CPUs need to have an increased operation speed.
In synchronous (clock-synchronized) memories, command inputs (or address inputs) are entered such as to satisfy a setup time and a hold time relative to a rising edge of an external clock signal. The input commands latched by latch circuits (edge-triggered latches) provided at the first stage are held for 1tCK (tCK: one clock cycle), and are decoded by a decoder during this data hold time.
FIG. 1
is a drawing showing a related-art configuration of input circuits and decoders.
FIG. 2
is a timing chart showing an operation of the configuration of FIG.
1
.
The configuration of
FIG. 1
includes a latch
10
, a latch
11
, and a decoder
12
. The latch
10
includes a gated inverter
13
, an inverter
14
, and a gated inverter
15
. The latch
11
includes a gated inverter
16
, an inverter
17
, and a gated inverter
18
. One set of the latch
10
and latch
11
is provided for each of incoming signals in
0
and in
1
.
The latch
10
receives a complementary signal intCLK_c that is complementary to a clock signal intCLK_t, and the latch
11
receives the clock signal intCLK_t. When the clock signal intCLK_t is LOW (when the complementary signal intCLK_c is HIGH), the gated inverter
13
of the latch
10
inverts the incoming signal in
0
(or in
1
), and supplies the inverted signal to a latch circuit
20
that is formed by the inverter
14
and the gated inverter
15
. When clock signal intCLK_t changes to HIGH, the latch circuit
20
latches the incoming signal. At this time, the gated inverter
16
of the latch
11
is open, so that the signal that is latched by the latch circuit
20
is output through the latch
11
as latched signals in
0
lat and in
1
lat. When the clock signal intCLK_t thereafter turns to LOW, the gated inverter
16
closes, and the incoming signal is latched by a latch circuit
21
that is formed by the inverter
17
and the gated inverter
18
. Even when a next incoming signal arrives at the latch
10
during the period in which the clock signal intCLK_t is LOW, the preceding incoming signal latched by the latch circuit
21
will be held there until the clock signal intCLK_t is set to HIGH.
In this manner, as shown in
FIG. 2
, the latched signals in
0
lat and in
1
lat obtained by latching the incoming signals are held for the duration of the period 1tCK (tCK: one clock period). Within this period, the decoder
12
of
FIG. 1
decodes the latched signal in
0
lat and in
1
lat, and outputs output signals out<0:3> as results of the decoding.
In order to determine the incoming signals before the latch
10
latches the incoming signals, the setup time needs to be secured as shown in FIG.
2
. In the configuration described above, the decoding time for the decoder
12
to decode the incoming signals is necessary in addition to the setup time. Accordingly, a delay equivalent to the sum of the setup time and the decoding time is incurred before the decoding results are obtained from the incoming data signals.
In order to obviate this problem, a scheme has been devised to utilize the setup time to complete the decoding operation before the latch operation.
FIG. 3
is a drawing showing a related-art configuration of command (or address) input circuits and a decoder which achieves speed enhancement by utilizing the setup time.
FIG. 4
is a timing chart showing an operation of the configuration of FIG.
3
. As shown in FIG.
3
and
FIG. 4
, the decoder
12
in this configuration is situated at a stage preceding the latches
10
and
11
, and carries out its decoding operation within the setup time of the latches, thereby achieving the speed enhancement.
In this configuration, however, a large number of latches are necessary since a large number of decoded signals need to be latched separately. When 2-bit inputs are to be decoded as shown in
FIG. 3
, for example, 8 latches in total are necessary. When 3-bit inputs are to be decoded, 16 latches in total are necessary.
In this configuration, further, a timing adjustment circuit
22
is used to delay a clock signal, thereby setting the latch timing to a proper timing that takes into account the decoding time of the decoder. Since the timing adjustment circuit
22
may suffer timing deviation due to a product variation, power supply potential fluctuation, etc., there is a need to secure a large timing margin.
The related-art configuration shown in
FIG. 3
, therefore, results in an increase of chip size, and may not be able to achieve a sufficient speed enhancement because of the need to secure a large timing margin that takes into account timing deviation caused by a product variation, power supply potential fluctuation, etc. Further, if a large timing margin is given to the setup time, the timing margin for the hold time will have to be decreased. In general, the setup time and the hold time shorten as the clock cycle shortens. In the systems having an increased clock speed, thus, it is difficult to secure a sufficient timing margin.
Accordingly, there is a need for a semiconductor device in which the speed of a first-stage input latch is increased without increasing chip size.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor device according to the present invention includes a first latch which receives an input signal, and holds the input signal during a half cycle period of a first clock signal, a delay element coupled to an output of the first latch, a second latch which is coupled to an output of the delay element, and holds a signal output from the delay element during a half cycle period of a second clock signal, and a circuit which adjusts at least one of the first clock signal and the second clock signal such that the signal latched by the first latch during the half cycle period of the first clock signal is latched via the delay element by the second latch during the half cycle period of the second clock signal that follows the half cycle period of the first clock signal.
In the semiconductor device as described above, the delay element may be a decoder, for example. In this example of the present invention, the decoder is situated between the two latches together forming an edge-trigger circuit, and carries out the decoding operation by utilizing the setup time, thereby hiding a time delay caused by the decoding operation. In this configuration, it suffices to have the first-stage latches only as many as there are incoming signals, so that a high-speed latch-&-decode operation can be achieved through a smaller number of circuit elements than in the related-art configuration. Further, the timing adjustment of clock signals makes it possible to achieve reliable data transfer from the first latch to the second latch.
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