Semiconductor device with gate space of positive slope and...

Details Semiconductor device with gate space of positive slope and... Semiconductor device with gate space of positive slope and...

2005-11-29

2005-11-29

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S978000

Reexamination Certificate

active

06969673

ABSTRACT:
Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.

REFERENCES:
patent: 4676869 (1987-06-01), Lee et al.
patent: 5858865 (1999-01-01), Juengling et al.
patent: 5879459 (1999-03-01), Gadgil et al.
patent: 6391803 (2002-05-01), Kim et al.

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