Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-25
2004-11-09
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S282000, C257S285000, C257S286000, C257S288000, C257S327000, C257S344000, C257S345000, C257S346000, C257S348000, C257S350000, C257S351000, C438S282000, C438S309000, C438S311000
Reexamination Certificate
active
06815765
ABSTRACT:
TITLE OF THE INVENTION
Semiconductor Device with of Modulating Gain Coefficient and Semiconductor Integrated Circuit Including the Same
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device structure that relieves a limit of miniaturization due to physical constraints of the device structure in a semiconductor integrated circuit (e.g. LSI: Large Scale Integrated circuit), and a configuration of a semiconductor integrated circuit having the device as a component.
2. Description of the Background Art
Semiconductor integrated circuits represented by LSI have improved in performance, i.e., increase in integration and speed, and reduction in power consumption, by mainly miniaturizing devices for over thirty years since its manufacturing technology was established.
In these days when a minimum wiring width indicating the level of device miniaturization have reached 0.15 &mgr;m, however, various constraints due to physical phenomenon have become obvious in the device miniaturization. The minimum wiring width generally corresponds to a gate length L of a transistor. Such constraints makes it difficult to further miniaturize devices by the conventional technique, meaning that improvement in LSI performance by the device miniaturization can no longer be expected in the conventional trend.
First, the outline and future problems of the conventional miniaturization technique of semiconductor devices will be described.
FIG. 26
schematically shows an example in which a device is miniaturized according to a constant electric-field scaling law, the most popular rule for MOS (Metal Oxide Semiconductor) transistors.
FIG. 26
(
b
) illustrates an MOS transistor which is reduced to a scale of one-half of the device shown in
FIG. 26
(
a
). Important parameters for determining the characteristic of the MOS transistor includes, as shown in
FIG. 26
(
a
), a gate length L, a gate width W, a thickness of an insulation film (a thickness of a gate oxide film) T
OX
, a diffusion depth of source and drain X
j
, a concentration of impurities introduced at a substrate or a channel portion directory below the gate, and a power-supply voltage V
d
.
TABLE 3
Scaling Law for Device
Constant electric-field
T
ox
constant proportional
Parameter
proportional scaling down
scaling down
Gate length L
1/&agr;
1/&agr;
Gate width W
1/&agr;
1/&agr;
Thickness of
1/&agr;
1
oxide film T
ox
Junction depth X
1
1/&agr;
1/&agr;
Impurity con-
&agr;
&agr;
centration N
Voltage Vd
1/&agr;
1/&agr;
A scaling law for these parameters is, as indicated in the middle column in Table 3, the constant electric-field scaling law where L, W, T
OX
, X
j
and V
d
, are reduced by an inverse of a scaling parameter &agr; and only N is multiplied by &agr;.
According to the constant electric-field scaling law, the magnitude of the electric field is constant irrespective of size reduction of the device. MOS transistors and the like have a constraint in that the electric field within the device (in particular, in the drain or the like) cannot be increased to prevent hot carriers from increasing in order to ensure reliability.
As a physical phenomenon, however, current starts to flow between the substrate (or the channel portion directly below the gate) and a gate electrode when thickness of insulation film (thickness of gate oxide film) T
OX
becomes thinner than approximately 3 nm. Thus, the thickness of the gate oxide film cannot be made thinner than approximately 3 nm because of the physical constraint of tunnel current. Thickness of insulation film (thickness of gate oxide film) T
OX
of 3 nm corresponds with gate length L of approximately 0.12 &mgr;m.
If gate length L is approximately 0.12 &mgr;m or shorter, miniaturization must be performed according to an irregular constant electric-field scaling law in which only thickness of insulation film (thickness of gate oxide film) T
OX
is constant, as indicated in the rightmost column in Table 3. Moreover, it is required for an MOS transistor to suppress its short channel effect in order to accurately operate as a switch device. For that purpose, diffusion depth X
j
of the source and drain must be reduced by a factor of 1/&agr;, while the concentration of introduced impurities must be increased so as to lower the electric resistance, in order to prevent deterioration of drivability of the source and drain. Furthermore, because the source and drain are formed by diffusion, it had gradually been difficult to reduce diffusion depth X
j
at a rate of 1/&agr; if diffusion depth X
j
becomes smaller than several tens of nm.
In recent years, therefore, effective reduction of diffusion depth X
j
(i.e. suppress of the short channel effect) has been expected by a so-called fully-depleted SOI (Silicon On Insulator) device in which an Si thin film is formed on an insulation film and a transistor is formed thereon. For practical application of the SOI device, however, a backstage effect, a substrate potential floating, a parasitic bipolar effect and the like must be newly addressed, leaving some technical issues to be solved.
Here, assuming that diffusion depth X
j
can be effectively reduced at a rate of 1/&agr; by e.g. the fully-depleted SOI device, and that the irregular constantelectic-filed scaling down can be performed where only thickness of insulation film (thickness of gate oxide film) T
OX
is constant when gate length L is 0.12 &mgr;m or shorter, the trend of the LSI performance is estimated in the device miniaturization.
FIG. 27
shows a conventional trend of device miniaturization, with consideration given to the physical constraints for thickness of insulation film (thickness of gate oxide film) T
OX
.
Referring to
FIG. 27
, it is assumed that C
OX
is a gate capacitance which is inversely proportional to thickness of insulation film (thickness of gate oxide film) T
OX
, and that a dielectric constant &egr; of the insulation film is constant. Since the drivability of the device is proportional to gate capacitance C
OX
, improvement in performance can be expected by multiplying dielectric constant &egr; of the insulation film by &agr; even if thickness of insulation film (thickness of gate oxide film) T
OX
is constant. To change dielectric constant &egr; of the insulation film, however, the material for the insulation film must be changed, which appears to be difficult in practical application.
TABLE 4
Scaling law for Wiring
&sgr; constant
proportional scaling
Proportional scaling
Parameter
down
down
Wiring length l
1/&agr;
1/&agr;
Wiring width w
1/&agr;
1/&agr;
Thickness of wiring &
1/&agr;
1/&agr;
interlayer film k,t
Wiring material con-
1
&agr;
ductivity &sgr;
Wiring resistance Rm
wk
&agr;
1
&sgr;/l
Wiring capacitance Cm
lw/t
1/&agr;
1/&agr;
Wiring delay time
1
1/&agr;
Tm
CmRm
Table 4 shows a scaling law for wiring. In order to improve the LSI performance, reduction in the area of wiring that is proportional to the area reduction of the device must be realized for a higher degree of integration. As to increase in operation speed and reduction in power consumption, a wiring capacitance must be reduced. The wiring had conventionally been scaled down without a change of a wiring material (e.g. Al), i.e., with constant electric conductivity &sgr;. Recently, however, a material such as Cu (copper) is introduced in an attempt to increase electrical conductivity &sgr; in order to avoid a revealed wiring delay, i.e., the wiring capacitance being larger with respect to a device capacitance such as a gate capacitance, hindering improvement in the LSI performance. Moreover, a method of making the thickness of wiring or interlayer film larger than that in the scaling rule has been considered. In any case, in the scaling law of wiring, the wiring capacitance that greatly affects a signal delay is expected to be reduced by a factor of 1/&agr;, as indicated in Table 4.
As to the device and wiring, according to the scaling laws indicated in Tables 3 and 4,
Exploitation of Next Generation Co. Ltd.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Ortiz Edgardo
Wilson Allan R.
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