Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1997-06-06
2002-09-03
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S778000, C257S786000, C438S014000, C438S018000, C438S612000, C438S666000, C029S593000
Reexamination Certificate
active
06445001
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device with a flip-chip structure, in which semiconductor elements (chips) are connected to a circuit board via protruding electrodes such as solder bumps, and a method of manufacturing the same.
Conventionally, in order to mount semiconductor elements on a circuit board, the following methods are used. That is, the distal ends of a plurality of lead lines extending from each semiconductor element (to be referred to as a chip hereinafter) are electrically connected to a wiring or interconnect pattern on a circuit board, or a chip is mounted on a circuit board and is electrically connected thereto by wire bonding, TAB (Tape Automated Bonding), or the like.
However, in the former method in which lead lines are extended from the chip and are connected to the circuit board, the interval between adjacent bumps is limited, thus posing a serious bottleneck against realization of high packaging density of semiconductor devices.
Especially, in recent years, semiconductor devices are used in a variety of applications, and their packaging densities are increasing. For example, a low-profile circuit board such as a memory card is often used, and the number of memory elements to be mounted is on the rise.
Under such circumstances, packaging chips using lead lines has limitations.
In view of this problem, a flip-chip structure has received a lot of attention. In this structure, bumps are attached to a plurality of connection electrodes (pads) formed on a chip, and are directly connected to the wiring pattern on the circuit board.
FIG. 1
is a sectional view of a conventional semiconductor device in which a chip consisting of a silicon semiconductor is mounted on a circuit board by flip-chip bonding.
FIG. 2
is a plan view showing the major surface of a semiconductor substrate, that has bumps, and
FIG. 3
is a sectional view showing the structure of input/output terminals having bumps.
A semiconductor substrate
1
comprises pad electrodes
7
and bumps
3
. Each pad electrode
7
is used as a pad electrically connected to an internal integrated circuit on the major surface of the semiconductor substrate
1
, and consists of, e.g., aluminum.
Each bump
3
is connected on the pad electrode
7
, is made up of a low-melting point metal solder bump containing lead (Pb), tin (Sb), and the like as major components, and has a height of about 100 &mgr;m.
Each input/output terminal
10
formed on the major surface of the conventional semiconductor substrate
1
shown in
FIG. 2
comprises a bump
3
and a pad electrode
7
, as shown in
FIG. 3
(to be explained later) and a barrier metal
9
is normally interposed between the bump
3
and the pad electrode
7
.
At least one chip is mounted on a circuit board
2
. A plurality of bumps
3
on the semiconductor substrate
1
are electrically connected to pad electrodes (to be referred to as substrate pads hereinafter)
8
connected to a wiring pattern (not shown) formed on the surface of the circuit board
2
, thus mounting the semiconductor substrate
1
on the circuit board
2
.
Each bump
3
may use gold in addition to the low-melting point metals, or may also use a structure prepared by forming a conductive layer on the surface of a spherical insulating member. As the low-melting metals, Pb—Sn solder, In—Sn solder, and the like are known.
As the circuit board
2
, a printed board prepared by stacking glass base members impregnated with an epoxy resin, a ceramic board, a silicon semiconductor board, and the like are used. Also, an encapsulating resin may be filled between the semiconductor substrate
1
and the circuit board
2
.
The major surface of the semiconductor substrate
1
is divided into an inner region
1
a
and a peripheral region
1
b
. On the inner region
1
a
, an integrated circuit
20
as an internal circuit formed inside the semiconductor substrate
1
is formed. An input/output circuit
11
is formed on that region of the peripheral region
1
b
, which is in the vicinity of the inner region
1
a
, and the input/output terminals
10
are electrically connected to the integrated circuit
20
via the input/output circuit
11
.
The bump structure on the semiconductor substrate is as shown in FIG.
3
. That is, a pad
7
of, e.g., aluminum, which is electrically connected to the integrated circuit formed inside the semiconductor substrate, is formed on an insulating film
4
formed on the surface of the semiconductor substrate
1
. The surrounding portion of the pad
7
is protected by an insulating film
5
of, e.g., SiO
2
.
An opening portion or via hole
5
a
of the insulating film
5
is formed on the surface of the pad
7
to expose the pad
7
therefrom. This opening portion
5
a
is covered by a barrier metal
9
, which is electrically connected to the pad
7
. A bump
3
is attached on the barrier metal
9
. The barrier metal
9
consists of, e.g., Pd/Ni/Ti, TiW, Ti/Ti/W, or the like.
As described above, the input/output terminals of the conventional semiconductor device with the TAB or flip-chip structure are formed on the peripheral region along the outer edge of the semiconductor substrate.
Defect discrimination of an integrated circuit in the chip or wafer state (to be referred to as die testing hereinafter) is done by electrical tests by bringing probes
6
projecting from a probe card
12
into contact with the bumps
3
on the input/output terminals
10
, as shown in FIG.
4
.
However, in recent years, semiconductor devices having the same functions as those of conventional ones can be realized in smaller sizes along with advance of the micropatterning techniques of elements, while it has become harder to decrease the pitch of input/output terminals due to limitations traced to the interconnection techniques.
As a consequence, the number of input/output terminals formed on the outer peripheral portion of the semiconductor substrate is insufficient, and a structure in which a plurality of input/output terminals are arranged on the entire major surface of the semiconductor substrate
1
is proposed, as shown in FIG.
5
. The input/output terminals of a chip are arranged on the inner region where the integrated circuit is formed, and the peripheral region of the major surface of the semiconductor substrate
1
.
However, the chip with such structure suffers the following problem.
That is, die testing is conducted using the probes projecting from the conventional probe card, but the probes cannot be simultaneously in contact with all the plurality of input/output terminals on the entire major surface.
In order to solve this problem, a probe card that can set a plurality of probes on the entire major surface of the semiconductor substrate is required. When a probe card with such structure is used, it is very hard to attain alignment between a plurality of bumps on the input/output terminals of the semiconductor substrate and the plurality of probes, thus posing another problem.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its object to provide a semiconductor device which comprises die testing terminals and input/output terminals with a structure that allow easy die testing even by a conventional probe card using probes, and a method of manufacturing the same.
In order to achieve the above object, a semiconductor device according to the present invention comprises:
a semiconductor substrate;
an input/output terminal portion formed on the semiconductor substrate, the input/output terminal portion having a plurality of input/output terminals formed on an inner region on the semiconductor substrate, and a plurality of die testing terminals formed on a peripheral region on the semiconductor substrate; and
a metal wiring layer for connecting the input/output terminals and the die testing terminals.
Also, a method of manufacturing a semiconductor device according to the present invention, comprises the steps of:
forming a multilayered wiring structure on a semiconductor substrate;
f
Chambliss Alonzo
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Talbott David L.
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