Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-09-17
2003-04-01
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030
Reexamination Certificate
active
06542420
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device with a flexible redundancy system for saving a defective memory cell.
Semiconductor devices have a redundancy system. To enhance the yield of products, the redundancy system saves a defective memory cell, if any, by replacing it with a redundancy cell. The redundancy system that is most generally used at the present stage performs such replacement in units of a cell array, more specifically in units of a plurality of rows or columns (there is a case where it is done in units of one row or column). If in this system, a defective memory cell is found after a test, a cell array including the defective cell is replaced with a-redundancy cell array (spare element) of the same size.
Address information on a cell array including the defective cell is stored in a non-volatile storage element. A fuse is generally used as the storage element at the present stage. Since the address information is usually formed of several bits, a fuse set which includes a plurality of fuses corresponding to the address information is a unit of redundancy. Further, usually, one spare element corresponds to one fuse set, and the same number of fuse sets as:the spare elements are employed in a chip. When using a spare element, a fuse included in a fuse set corresponding thereto is cut. Since this system is of a simple structure, it is widely used now.
On the other hand, the redundancy system requires a spare element and a fuse set in addition to a usual circuit, and hence requires a large chip area. In light of the fact that the area of a redundancy circuit and the number of defective cells which the redundancy circuit can save have a trade-off relationship, various types of redundancy systems are now proposed for enhancing the area efficiency. For example, Kirihata et al. propose a flexible redundancy system (see “Fault-Tolerant Designs for 256 Mb DRAM” (IEEE JOURNAL of SOLID-STATE CIRCUITS, VOL. 31, NO. 4, April 1996)). Since in this system, a single spare element covers a wide cell array area, even when defective cells exist in only a part of a chip, they can be saved in a similar manner to a case where defective cells are uniformly dispersed within a cell array. Accordingly, the number of spare elements can be reduced, thereby increasing the area efficiency of the redundancy circuit.
As described above, where the number of defective cells per one chip is detected or can be estimated, to save them using a small number of spare elements can increase the area efficiency and hence be more effective. In particular, where a single spare element can cover a wide cell array area, the above system is effective.
However, memory chips in which a memory cell array is divided into portions have been developed. For example, there is a memory chip provided with a plurality of banks which are simultaneously activated. This type of memory chip cannot have a spare element for saving a defective cell which is included in any other bank. The larger the number of banks, the larger the number of divisions of a memory cell array, and the narrower the cell array area that each spare element can cover. Although this is mainly a problem of a row spare element, a similar problem will occur with a column spare element. Moreover, if in memory devices operable at high speed, the distance between a memory cell and another replaced by a spare element becomes longer than before the replacement, transmission delay of a signal or data becomes greater, thereby degrading the high speed operability. On the other hand, to maintain the high speed operability, replacement must be performed between memory cells located close to each other. This means that the column spare element cannot cover a wide cell array area.
When the spare element can cover only a narrow range from the limitations such as the number of banks, a spare element must be provided in units of one narrow cell array area to save even defective cells located at only a part of a memory cell. This means that a great number of spare elements, which significantly exceeds the average number of defective cells, must be incorporated in one chip, thereby degrading the area efficiency. Moreover, in the conventional system in which one spare element corresponds to one fuse set, the number of fuse sets inevitably increases with an increase in the number of spare elements. Since, in general, fuses require a larger area than spare elements, the system in which one spare element corresponds to one fuse set results in a large decrease in the area efficiency of the redundancy circuit.
BRIEF SUMMARY OF THE INVENTION
This invention has been developed to solve the above-described problems, and has its object to provide a semiconductor device that employs a redundancy circuit of a high saving efficiency and a high area efficiency on a chip, in which the redundancy circuit requires only a small number of non-volatile storage elements to save a defective memory cell.
The object is realized by a device described as below.
A semiconductor storage device comprising: a memory cell array having memory cells arranged in columns and rows, the memory cell array being-divided into a plurality of sub cell arrays; redundancy cell arrays each located adjacent to a corresponding one of the sub cell arrays; row decoders for each selecting a corresponding one of the rows of the memory cell array in accordance with an input address; column decoders for each selecting a corresponding one of the columns of the memory cell array in accordance with an input address; a plurality of storage circuits for storing addresses assigned to defective memory cells included in the memory cell array, and also storing mapping information indicative of the relationship between the storage circuits and the redundancy cell arrays, the storage circuits outputting, when an address assigned to one of the defective memory cells stored therein matches an input address, a replacement control signal for the defective memory cell on the basis of the result of matching, and the mapping information; and spare decoders each to be activated by the replacement control signal supplied from the storage circuits to thereby select a corresponding one of the redundancy cell arrays.
Furthermore, the object of the invention is realized by a device as below.
A semiconductor storage device comprising: a memory cell array having memory cells arranged in columns and rows, the memory cell array being divided into a plurality of sub cell arrays; redundancy cell arrays each located adjacent to a corresponding one of the sub cell arrays; row decoders for each selecting a corresponding one of the rows of the memory cell array in accordance with an input address; column decoders for each selecting a corresponding one of the columns of the memory cell array in accordance with an input address; a plurality of storage circuits each: including: a plurality of first storage elements for storing addresses assigned to defective memory cells included in the memory cell array; a plurality of second storage elements for storing mapping information which indicates the relationship between the redundancy cell arrays and the storage circuits; a plurality of comparators each for comparing the address of a corresponding one of the defective memory cells stored in a corresponding one of the first storage elements with an input address, and outputting, when the stored address matches the input address, a signal indicating that those addresses match each other; and a decoder for decoding the mapping information stored in the second storage elements when each of the comparators has output the signal indicating that the addresses match each other; and spare decoders each to be activated by the output signal of the decoder to thereby select a corresponding one of the redundancy cell arrays.
In the invention, defective cells can be saved in a reliable manner even when they are located at only one area of the memory cell array, by virtue of the structure in which the redundancy cell arrays and mapping informatio
Banner & Witcoff , Ltd.
Tran M.
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