Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-03-29
2011-03-29
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S413000, C257S329000, C257SE29274
Reexamination Certificate
active
07915693
ABSTRACT:
A semiconductor device according to an embodiment includes: a semiconductor substrate; a fin formed on the semiconductor substrate; a gate electrode formed so as to sandwich both side faces of the fin between its opposite portions via a gate insulating film; an extension layer formed on a region of a side face of the fin, the region being on the both sides of the gate electrode, the extension layer having a plane faced to a surface of the semiconductor substrate at an acute angle; and a silicide layer formed on a surface of the plane faced to the surface of the semiconductor substrate at an acute angle.
REFERENCES:
patent: 7129550 (2006-10-01), Fujiwara et al.
patent: 7214576 (2007-05-01), Kaneko et al.
patent: 7314787 (2008-01-01), Yagishita
patent: 7425500 (2008-09-01), Metz et al.
patent: 7569489 (2009-08-01), Dyer et al.
patent: 2006/0166456 (2006-07-01), Fujiwara et al.
patent: 2007/0045736 (2007-03-01), Yagishita
patent: 2007/0075372 (2007-04-01), Terashima et al.
patent: 2007/0241399 (2007-10-01), Irisawa et al.
patent: 2007/0257296 (2007-11-01), Miyano
patent: 2008/0003755 (2008-01-01), Shah et al.
patent: 2008/0121998 (2008-05-01), Kavalieros et al.
patent: 2005-86024 (2005-03-01), None
patent: 2005-294789 (2005-10-01), None
patent: 2007-35957 (2007-02-01), None
patent: 2007-73831 (2007-03-01), None
Jakub Kedzierski, et al., “Extension and Source/Drain Design for High-Performance FinFET Devices”, IEEE Transactions on Electron Devices, vol. 50, No. 4, Apr. 2003, pp. 952-958.
A. Kaneko, et al., “Sidewall Transfer and Selective Gate Sidewall Spacer Formation Technology for Sub-15nm FinFET with Elevated Source/Drain Extension”, IEEE, 2005, 4 pages.
T. Kanemura, et al., “Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations”, IEEE, SISPAD, 2006, pp. 131-134, 2006.
Budd Paul A
Jackson, Jr. Jerome
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
LandOfFree
Semiconductor device with fin and silicide structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with fin and silicide structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with fin and silicide structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2662682