Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-01-23
2001-11-20
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
Reexamination Certificate
active
06320805
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device provided with external pins for input and/or output of signals.
2. Description of the Background Art
Conventionally, a semiconductor integrated circuit device provided with a large number of external pins incorporates therein a test circuit for detecting contact failure between respective external pins and board interconnection when mounted on a board.
In a conventional testing method, a signal of an H level is applied to board interconnection, and when the signal at the H level is transmitted via an external pin to a test circuit, it is determined that the contact state of the board interconnection and the external pin is normal. When the signal at the H level is not transmitted to the test circuit via the external pin, the determination is made that the contact between the board interconnection and the external pin is defective.
When a contact resistance value between the board interconnection and the external pin is several ohms, signal transmission timing is delayed by several ten ps, thereby reducing a signal voltage by several ten mV. This poses substantially no problem on a conventional semiconductor integrated circuit device. However, it may cause a fatal problem for a high-speed device such as a DDR SDRAM (double date rate, synchronous dynamic random access memory).
Further, with such a high-speed device, an error in determination of good/defective product may occur at a test before shipment, due to the contact resistance value between the external pin and a socket of a tester.
The same problem may arise when neighboring two external pins are electrically conducted to each other at a high resistance value.
The conventional testing method would only make a digital determination whether the contact state between the external pin and the board interconnection or the socket is normal. Such method is insufficient for testing of the high-speed device.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor device that allows detection of a contact resistance value between an external terminal and an external pin.
Another object of the present invention is to provide a semiconductor device that allows detection of a resistance value between external pins.
A semiconductor device according to the present invention is provided with a resistance detecting circuit for detecting a contact resistance value between an external terminal and an external pin in a test mode. Thus, it becomes possible to detect the contact resistance value between the external terminal and the external pin.
Preferably, in the test mode, a power supply potential is supplied to the external terminal. The resistance detecting circuit includes: a first transistor connected between the external pin and a first node and allowing a current of a value corresponding to the contact resistance value to flow therethrough; a second transistor connected between a line of power supply potential and a second node and allowing a current of a prescribed value to flow therethrough; first and second diode elements respectively connected between the first and second nodes and a line of a reference potential; and a comparison circuit comparing potentials at the fist and second nodes and, based on the comparison result, outputting a signal at a level corresponding to the contact resistance value. In this case, the potential at the first node decreases as the contact resistance value increases. Thus, by comparing the potentials at the first and second nodes, the contact resistance value can be obtained.
Still preferably, in the test mode, a power supply potential is supplied to the external terminal. The resistance detecting circuit includes: a first transistor connected between the external pin and a first node and allowing a current of a value corresponding to the contact resistance value to flow therethrough; a second transistor connected between a line of power supply potential and a second node and allowing a current of a prescribed value to flow therethrough; and a current mirror circuit connected between the first and second transistors and a line of reference potential and outputting a signal at a level corresponding to the contact resistance value. In this case, again, the current flowing through the first transistor decreases as the contact resistance value increases. Thus, by comparing the current values flowing through the first and second transistors, it becomes possible to obtain the contact resistance value.
Still preferably, a plurality of external pins are provided, and a resistance detecting circuit is commonly provided for the plurality of external pins. Further, a switching circuit is provided, which selects any external pin from the plurality of external pins and couples the selected external pin to the resistance detecting circuit. In this case, one resistance detecting circuit can detect the contact resistance values of the plurality of external pins.
Still preferably, a monitor pin is further provided, which externally guides an output signal of the resistance detecting circuit. In this case, it becomes readily possible to monitor the output signal of the resistance detecting circuit.
Still preferably, a plurality of sets of external pins and resistance detecting circuits are provided, and further, a monitor pin for externally guiding the output signal of the resistance detecting circuit, and a switching circuit for selecting any resistance detecting circuit from the plurality of resistance detecting circuits and supplying the output signal from the selected resistance detecting circuit to the monitor pin are provided. In this case, it is possible to monitor the output signals from the plurality of resistance detecting circuits with a single monitor pin.
Another semiconductor device according to the present invention is provided with a resistance detecting circuit for detecting a resistance value between a first external pin and a second external pin in a test mode. Thus, it becomes possible to detect the resistance value between the two external pins.
Preferably, in the test mode, a power supply potential is supplied to the first external pin. The resistance detecting circuit includes: a first transistor connected between the second external pin and a first node and allowing a current of a value corresponding to the resistance value between the first and second external pins to flow therethrough; a second transistor connected between a line of power supply potential and a second node and allowing a current of a prescribed value to flow therethrough; first and second diode elements respectively connected between the first and second nodes and a line of a reference potential; and a comparison circuit comparing potentials at the first and second nodes and, based on the comparison result, outputting a signal of a level corresponding to the resistance value between the first and second external pins. In this case, the potential at the first node decreases as the resistance value between the first and second external pins increases. Thus, it becomes possible to obtain the resistance value between the first and second external pins by comparing the potentials at the first and second nodes.
Still preferably, in the test mode, a power supply potential is supplied to the first external pin. The resistance detecting circuit includes: a first transistor connected between the second external pin and a first node and allowing a current of a value corresponding to the resistance value between the first and second external pins to flow therethrough; a second transistor connected between a line of power supply potential and a second node and allowing a current of a prescribed value to flow therethrough; and a current mirror circuit connected between the first and second nodes and a line of reference potential and outputting a signal of a level corresponding to the resistance value between the first and second externa
Sakamoto Wataru
Yamaoka Shigeru
Le Vu A.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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