Semiconductor device with embedded memory cells

Details Semiconductor device with embedded memory cells Semiconductor device with embedded memory cells

1999-10-07

2002-09-24

Le, Dieu-Minh (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S733000, C714S734000

Reexamination Certificate

active

06457141

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with embedded memory cells, and more particularly to a semiconductor device with embedded memory cells which can perform tests, a direct access test with a memory tester and a built-in self test with an embedded test circuit, without changes in probing between the semiconductor device and a memory tester.
2. Description of the Related Art
The semiconductor device with embedded memory cells comprises a logic block, a memory block and an embedded test circuit block. In the semiconductor device, the memory tester tests the memory block in the direct access test mode. On the other hand, the logic tester tests the logic block and the embedded test circuit block tests the memory-block in the built-in self test mode, i.e., BIST.
Thus, a conventional semiconductor device with embedded memory cells comprises separate pins: the pins (or pads) used for performing a direct access test on the memory block with a memory tester; and the pins (or pads) used for performing a built-in self test on the logic block and the memory block with a logic tester.
In other words, the direct access test and the built-in self test are used together to test the memory block of the semiconductor device with embedded memory cells.
In order to analyze a defect of the memory block detected in the built-in self test with a logic tester it is necessary to simultaneously perform the direct access test and the built-in self test with a memory tester.
However, there is a problem in the conventional semiconductor device with embedded memory cells in that it is necessary to modify the connection of pins between the memory tester and the semiconductor device when performing the respective tests, because the pins are separately installed for the direct access test mode and the built-in self test mode.
FIG. 1
is a block diagram for illustrating the conventional semiconductor device with embedded memory cells. The semiconductor device
100
comprises a logic block
10
, a memory block
20
, an embedded test circuit block
30
, multiplexers
40
,
42
,
44
,
46
,
48
and pads
50
,
52
,
54
,
56
,
58
,
60
,
62
.
The functions of respective blocks will be described below. The logic block
10
inputs and outputs data between the memory block
20
, thereby performing specific functions that are designed by a designer. The memory block
20
writes and reads data in response to addresses or control signals. The embedded test circuit block
30
responds to BIST control signals sent from outside the device and generates internal addresses, control signals and data signals to write and read data to the memory block
20
. The embedded test circuit block
30
also determines whether the read data is identical to the written data and sends the test results about the functional states of the memory block
20
out of the semiconductor device. The pad
50
is used only in the normal operation mode, but not in the test modes. The pad
52
is a control pad to transmit control signals for changing modes between normal operation, the direct access test and the built-in self test. The pad
54
inputs and outputs data with the logic block
10
in the normal operation mode, and transmits addresses to the memory block
20
in the direct access test mode. The pad
56
inputs and outputs data with the logic block
10
in the normal operation mode, and transmits control signals to the memory block
20
in the direct access test mode. The pad
58
inputs and outputs data with the logic block
10
in the normal operation mode, and inputs and outputs data with the memory block
20
in the direct access test mode. The pad
60
inputs and outputs data with the logic block
10
in the normal operation mode, and transmits BIST control signals to the embedded test circuit block
30
in the BIST mode. The pad
62
inputs and outputs data with the logic block
10
o operation mode, and outputs the test result generated from the embedded test circuit block
30
in the BIST mode.
The multiplexer
40
responds to mode control signals to input and output data between the pad
54
and the logic block
10
in the normal operation mode, and to transmit addresses from the pad
54
to the memory block
20
in the direct access test mode. The multiplexer
42
responds to the mode control signals to input and output data between the pad
56
and the logic block
10
in the normal operation mode, and to transmit control signals from the pad
56
to the memory block
20
in the direct access test mode. The multiplexer
44
responds to mode control signals to input and output data between the pad
58
and the logic block
10
in the normal operation mode, and to input and output data between the pad
58
and the memory block
20
in the direct access test mode. The multiplexer
46
responds to mode control signals to input and output data between the pad
60
and the logic block
10
in the normal operation mode, and to transmit BIST control signals from the pad
60
to the embedded test circuit block
30
in the direct access test mode. The multiplexer
48
responds to mode control signals to input and output data between the pad
62
and the logic block
10
in the normal operation mode, and to output the test result generated from the embedded circuit block
30
to the pad
62
in the direct access test mode. The multiplexers
40
,
42
,
44
,
46
,
48
are respectively constructed in the structure of a general
2
-
1
multiplexer.
Reference signs shown in
FIG. 1
will be described below. S symbolizes a respective signal in the drawings. S
1
is an input and output signal between the pad
50
and the logic block
10
. S
2
is a mode control signal. S
3
is a data input and output signal of the logic block
10
. Signals (S
8
a, b, c, d, e
) are those derived from the S
3
. Signals (S
4
a, b, c
) are input and output signals between the pads
54
,
56
,
58
and the logic block
10
in the normal operation mode. S
4
a
and S
4
b
are addresses and control signals transmitted from the pads
54
,
56
to the memory block
20
, and S
4
c
is a test result input and output signal between the pad
58
and the memory block
20
. S
5
a
is a BIST control signal transmitted from the pad
60
to the embedded test circuit block
30
, and S
5
b
is a test result signal transmitted from the embedded test circuit block
30
to the pad
62
. In the built-in self test mode S
7
a
and S
7
b
are respectively related to S
5
a
and S
5
b
. S
9
is a signal transmitted between the logic block
10
and the memory block
20
, and S
10
is a signal transmitted between the memory block
20
and the embedded test circuit block
30
. In the drawings these signals do not have one identical bit, but respectively a predetermined bit. Even if each of the pads
50
,
52
,
54
,
56
,
58
,
60
is respectively shown as one pad, it is not composed of a single pad but grouped by combining the predetermined number of pads with similar functions. The other pads without specific numerals belong to one of those represented in specific reference numerals.
First, the direct access test of the conventional semiconductor device with embedded memory cells will be described with reference to FIG.
1
. In the case of the direct access test, a mode control signal is transmitted from the memory tester (not shown) through the pad
52
to the multiplexers
40
,
42
,
44
,
46
,
48
. The multiplexers
40
,
42
,
44
output addresses, control signals and data signals to the memory block
20
. In the direct access test mode, signals are not input to the pads
50
,
60
,
62
. Therefore, the memory tester writes data through the pad
58
to the memory block
20
and reads the written data to determine whether they are identical to the written data for testing the operational states (normal or defective) of the memory block
20
. This direct access test is performed in accordance with the test procedures programmed in the memory tester.
The procedures of the direct access test are briefly described

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