Semiconductor device with DDR memory controller

Details Semiconductor device with DDR memory controller Semiconductor device with DDR memory controller

2011-03-22

2011-03-22

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000, C365S194000, C365S233100, C365S233110, C365S233130

Reexamination Certificate

active

07911858

ABSTRACT:
In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection signal, to a DDR memory as an operation clock signal. A master DLL circuit is configured to receive one of the plurality of clock signals which has a maximum frequency as a reference clock signal to determine a delay code. A slave delay circuit is configured to delay a strobe signal from the DDR memory based on the determined delay code to generate an internal strobe signal for a data signal from the DDR memory.

REFERENCES:
patent: 6665230 (2003-12-01), Shrader et al.
patent: 2003/0076125 (2003-04-01), McCord
patent: 2009/0085618 (2009-04-01), Schneider et al.
patent: 2009/0085623 (2009-04-01), Schneider et al.
patent: 2004-220643 (2004-08-01), None
Micron Technology Inc., “DDR SDRAM Functionality and Controller Read Data Capture,” DesignLine, 3Q 1999, p. 1-24, vol. 8, issue 3.

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