Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-07-08
2002-08-27
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000, C438S675000, C257S763000
Reexamination Certificate
active
06440844
ABSTRACT:
This application is based on Japanese patent applications No. HEI 9-182559 filed on Jul. 8, 1997 and No. HEI 10-191804 filed on Jul. 7, 1998, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more specifically, to a semiconductor device with copper (Cu) wiring and its manufacture method.
b) Description of the Related Art
Semiconductor integrated circuit devices are required to have higher integration density and higher operation speed. Copper wiring is proposed as a solution for the above because resistivity of copper is smaller than that of aluminum. However, various problems occur when manufacturing a semiconductor integrated circuit device having the copper wiring.
More precisely, it is difficult to pattern the copper wiring, as desired, by the reactive ion etching applied onto a patterned resist film formed on the copper wiring layer. A proposed method without such patterning includes steps of forming a trench or groove in an insulating layer, filling (inlaying) the trench with copper, and removing bulged copper on the insulating layer by polishing or the like.
It is also proposed a method for forming a multi-layer wiring having connection holes which are filled with copper plugs. In this method, the connection holes are formed in an insulating layer provided between two copper wiring layers, and the copper plugs are formed by chemical vapor deposition (CVD) or electrolytic plating. After the connection holes are filled with copper, bulged copper is polished to be removed.
Conventional techniques for forming the copper wiring still have various problems. For example, preferable wiring should have the electro-migration resistance while having smaller resistivity, however, the copper wiring formed by the conventional method does not always have a high electro-migration resistance.
The copper wiring should be bonded strongly to adjacent layers, however, bond strength is not always enough. It is desired that an insulating layer has a large resistivity while the wiring has a low resistivity, however, the resistivity of the insulating layer formed by the conventional method is not always large enough.
The insulating layer formed on a wiring formed with buried copper is not always flat, however, a flat insulating layer is desired for forming a conductive layer thereon.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for manufacturing a semiconductor device having excellent copper wiring.
It is another object of the present invention to provide a semiconductor device having excellent copper wiring.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a first insulating layer formed on said semiconductor substrate; a first trench having a bottom and sides formed in said first insulating layer from a surface thereof to a middle in a thickness of said first insulating layer; a first wiring layer including a main wiring layer buried in said trench, and substantially composed of copper; an interlayer insulating film covering said first wiring layer and said first insulating layer; a connection hole formed through said interlayer insulating film, and having a side surface formed of said interlayer insulating film, and a bottom surface formed of a surface of a connection region of said first wiring layer; a conductive plug filling said connection hole and including a buried conductor substantially composed of tungsten; a second insulating layer formed on said conductive plug and said interlayer insulating film; a second trench formed through said second insulating layer from a top surface to a bottom surface thereof, and having a bottom and a side, wherein a part of the bottom is a top surface of said conductive plug; and a second wiring layer filling said second trench and including a main wiring layer which is substantially composed of copper.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising the steps of: forming a first insulating layer on a semiconductor substrate; forming a first trench in a top surface of said first insulating layer; forming a first wiring layer, filling said first trench, including a main wiring layer which consists essentially of copper; forming an interlayer insulating film on said first insulating layer while covering said first wiring layer; forming a connection hole through said interlayer insulating film to expose said first wiring layer; filling said connection hole with a conductive plug including a buried conductor which essentially consists of tungsten; and forming a second wiring layer connected to said conductive plug, including a main wiring layer which essentially consists of copper.
There is provided a wiring which has a high electro-migration resistance while its resistivity is low, by connecting multi-layer wirings of copper or copper alloy with conductive plug including a buried conductor of tungsten.
According to a further aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a copper wiring layer, filling a trench formed in an insulating layer; removing said copper wiring layer on said insulating film to leave a copper wiring only in said trench; forming an interlayer insulating film having planarizing function on said insulating film, covering said copper wiring; and forming another copper wiring on said interlayer insulating film having the planarizing function. Steps can be generated upon removing extra copper layer, however, those steps will be absorbed in the interlayer insulating layer having the planarizing function.
According to a further aspect of the present invention, there is provide a method for manufacturing a semiconductor device comprising the steps of: forming copper wiring; reducing an oxide film on a surface of said copper wiring by heating said copper wiring to a temperature in a range of 250° C. to 450° C. in a reductive gas or by treating in a plasma of a reductive gas; forming a film of a material not containing oxygen on said copper wiring without exposing said copper wiring to atmosphere.
The upper layer strongly sticks to the copper layer because the natural oxide film on the surface of the copper layer is removed.
Low via resistance between the upper and lower copper layers can be obtained. Moreover the wiring withstands electro-migration better. Other layers such as an insulating layer on the copper wiring are prevented from being peeled off.
REFERENCES:
patent: 5600170 (1997-02-01), Sugiyama
patent: 5686760 (1997-11-01), Miyakawa
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5759906 (1998-06-01), Lou
patent: 5780358 (1998-07-01), Zhou et al.
patent: 5880018 (1999-03-01), Boeck et al.
patent: 5953634 (1999-09-01), Kajita et al.
patent: 5989983 (1999-11-01), Goo et al.
patent: 6-291201 (1994-10-01), None
Endo Koji
Futo Wataru
Hoshino Masataka
Izumi Kiyoshi
Misawa Nobuhiro
Armstrong, Westerman and Hattori, LLP.
Cao Phat X.
Fujitsu Limited
LandOfFree
Semiconductor device with copper wiring and its manufacture... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with copper wiring and its manufacture..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with copper wiring and its manufacture... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2953608