Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
1999-11-09
2002-10-01
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S737000, C257S738000
Reexamination Certificate
active
06459161
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with connection terminals in a grid array.
This application is based on Japanese Patent Application No. 10-336522, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In recent years, as the functions of electronic devices have been improved and their sizes have been reduced, it has become necessary to install semiconductor devices on a board at a high density.
To install the semiconductor devices on the board at a high density, BGA semiconductor devices, shown in
FIG. 10
, have bump electrodes C and D, such as solder balls, on the underside of a substrate to which a semiconductor device is to be mounted.
FIG. 10
shows the underside of the BGA semiconductor device to be mounted on the board.
The package of the BGA (ball grid array) semiconductor device (hereinafter referred to as the “BGA package”) has approximately the same size as a semiconductor chip, and is called a chip size package (CSP).
The BGA packages are used for various purposes, i.e., for logic LSIs (Large Scale Integration) such as a microcomputer, and ASICs (Application Specific Integrated Circuits). These logic LSIs may have different functions, depending on their types, i.e., different numbers of external terminals and various functions.
The number of the external terminals may be several hundreds, and a number of metal balls are arranged along the edges of the BGA package. The logic LSIs allow flexibility in designing the pin arrangement irrespective of the compatibility of the external terminals.
Meanwhile, generalized products, such as memories, have almost the same functions. Therefore, when the pin arrangement is predefined, the memories can be mounted irrespective of their manufacturer or storage capacity.
Even when the storage capacity is increased or the number of address lines or data lines is increased, the pin arrangement may be defined in expectation of increases in storage capacity. Then, the memory can be mounted in the same package without changing the pin arrangement. The pins are arranged around the center of the package in the form of a grid array. Even when the number of address lines or data lines is increased, a new grid pin may be only added around the array so that the original pin arrangement can be maintained. Thus, there are differences between logic LSIs and the generalized products.
The bump electrodes C at the four corners on the underside of the BGA semiconductor device, however, are affected by thermal stress, more than on other bump electrodes D, due to variation in temperature and a difference in coefficient of thermal expansion between the board and the substrate. The thermal stress may cause electrical or mechanical disconnection of the bump electrodes C between the mount board and the substrate.
Moreover, the bump electrodes C may receive impacts, more than the other bump electrodes D, due to dropping or bumping of the semiconductor device. The impact may cause electrical or mechanical disconnection of the bump electrodes C between the mount board and the substrate.
To avoid this, Japanese Patent Application, Second Publication No. Hei 3-38737 (hereinafter referred to as the “background art 1”) discloses reinforcing the bump electrodes C at the four corners of the array. Another background art (hereinafter referred to as the “background art 2”) discloses the technique using all the outermost bump electrodes C and D for reinforcement.
Because in the background art 1 the reinforcing bump electrodes are positioned at the four comers, stress may be concentrated on the bump electrodes, and they may be accidentally disconnected. Therefore, the reinforcing bump electrodes cannot achieve their purpose.
According to the background art 2, the reinforcing bump electrodes improve the strength. However, to connect the electrodes enclosed by the bump electrodes to a external device, many signal lines must be provided between the bump electrodes. As the number of the signal lines is increased, the signal lines must be thinner. Because of the thin signal lines, the resistance increases so that the electric characteristics deteriorate. The thin signal lines are easy to disconnect during a normal manufacturing process or when using a normal substrate material. To manufacture the thin signal lines, a process or a material suitable for fine manufacturing is indispensable, thus increasing the manufacturing costs.
Moreover, when all the outermost electrodes are reinforcing bump electrodes, the number of reinforcing balls increases, thus increasing the costs.
When the bump electrodes are provided around the center of the grid array balls, it is difficult to provide the signal lines between the electrodes, as described above. Even when the bump electrodes are provided around the center, stress does not frequently occur around this area, and therefore these bump electrodes may be ineffective. Meanwhile, the number of the bump electrodes is increased, thus increasing the costs.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device which can reliably connect bump electrodes to a mount board.
In one aspect of the invention, in the semiconductor device with an IC chip provided on one side of a substrate, a plurality of connection terminals are provided on the other side of the substrate, are electrically connected to the IC chip through electrical connecting devices, form a rectangular grid array, and are arranged in positions other than comers of the array. Additional terminals may be provided outside the grid array.
In another aspect of the invention, a plurality of connection terminals are provided on the second side of the substrate, are electrically connected to the IC chip, form a rectangular grid array, and additional terminals are provided outside the grid array.
The connection terminals are conductors electrically and mechanically connected to a board to which the semiconductor device is mounted. The conductors are made of solder or tin alloy. The additional terminals are made of non-conductive material.
The connection terminals are spherical, and parts of the spheres protrude from the second side of the substrate. Some of the connection terminals are not electrically connected to the IC chip.
The additional terminals are aligned along at least one of the row direction and the column direction. The connection terminals are excluded from the center of the grid array.
The connection terminals are arranged at a regular pitch P. The additional terminals are arranged at an interval of integer multiple of the pitch P or division of the pitch P by integer. An interval between the connection terminals and the additional terminal is integer multiple of P or division of P by integer.
At least one of the additional terminals is electrically connected to the IC chip. At least one of the additional terminals is an index terminal. The connection terminals are electrically connected to the IC chip through conductors provided in the substrate.
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Hiraoka Tetsuya
Hirata Masayoshi
Sato Mitsutaka
Suzuki Yasuhiro
Chaudhuri Olik
Ha Nathan W.
NEC Corporation
Sughrue & Mion, PLLC
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