Active solid-state devices (e.g. – transistors – solid-state diode – Plural dram cells share common contact or common trench
Reexamination Certificate
1999-08-26
2001-05-29
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Plural dram cells share common contact or common trench
C257S208000, C257S211000
Reexamination Certificate
active
06239500
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit capable of improving integration degree.
2. Description of the Related Art
In the following, a non-volatile memory will be described as an example which will not give any limitative sense to this invention.
It is always one target of a semiconductor integrated circuit to improve integration degree or density. This target is also applied to non-volatile memories such as EEPROM, flash EEPROM, and mask ROM.
FIGS. 5A and 5B
are equivalent circuit diagrams of a NAND type flash EEPROM and a NOR type flash EEPROM. In the NAND circuit shown in
FIG. 5A
, a plurality of memory transistors T
11
, T
21
, . . . , T
81
of eight bits are serially connected on the left side column, with the source and drain of adjacent transistors being connected in common. Select transistors SA
1
and SB
1
are connected to both ends of this column.
Similarly, on the right side column, memory transistors T
12
, T
22
, . . . , T
82
of eight bits are serially connected, and select transistors SA
2
and SB
2
are connected to both ends of this column. Bit lines BL
1
and BL
2
are connected to ones of select transistors SA
1
and SA
2
at the external areas thereof, and each memory transistor has no bit contact.
The memory transistor has a stacked type gate electrode including a floating gate and a control gate, whereas the select transistor has a general single gate electrode. Eight word lines WL
1
, WL
2
, . . . , WL
8
are connected to the control gates of first- to eighth-row memory transistors. Select lines SG
1
and SG
2
are connected to the gates of the select transistors.
Write/erase of each memory transistor is performed by draining/injecting electrons through tunneling. A read operation is performed by using serially connected eight memory transistors as one unit. Therefore, as compared to a NOR type, an access speed is lower. However, since the number of bit contacts is small, integration degree can be raised.
In the NOR type EEPROM shown in
FIG. 5B
, similar to the NAND type, although a plurality of transistors T
11
, T
21
, . . . are serially connected, the drains of memory transistors are connected to bit lines BL at every second bit and a source line SL is connected in common.
Data write is performed by applying a high electric field to the drain side and writing electrons into the floating gate through hot electron injection. Data erase is performed by draining electrons to the source line through tunneling.
In the NOR type EEPROM, each bit can be directly accessed so that an access time is short. However, since it is necessary to form one bit contact per two memory transistors, an occupied area becomes large and integration degree is inferior to the NAND type. Assuming the same cell capacity, it is generally said that the area of the NOR type is broader by about 20% than that of the NAND type.
If the threshold value of a channel region of a memory transistor is selectively changed and the stacked gate is changed to a single gate, a mask ROM can be formed. Similar to EEPROM, a NAND type and a NOR type of mask ROM can be formed.
A direct access to a transistor among a plurality of transistors requires a large substrate area and high integration is not easy.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of directly accessing any one of a plurality of transistors and raising integration degree.
It is another object of the present invention to provide a semiconductor integrated circuit having a novel wiring pattern.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a surface area of a first conductivity type; a field insulating film for defining a plurality of active regions disposed regularly in terms of two dimensions on a surface of the semiconductor substrate, each active region including one bit contact region and subsidiary active regions extending from the bit contact region in four directions; a plurality of first and second word lines, the plurality of first word lines extending as a whole in a first direction on the semiconductor substrate, the plurality of second word lines extending as a whole in a second direction on the semiconductor substrate, the first direction crossing the second direction, and in each active region two subsidiary active regions crossing the first word lines and remaining two subsidiary active regions crossing the second word lines; a plurality of bit lines crossing the first and second directions on the semiconductor substrate, each bit contact region being connected to a corresponding one of the bit lines; and an interlayer insulating region for insulating the first word lines, the second word lines, and the bit lines from one another.
Since the active region contains one bit contact region and subsidiary active regions extending in four directions from the bit contact region, four transistors can be connected to one bit contact. Since word lines connected to the gate electrodes of transistors extend in two directions crossing each other, four transistors connected to the common bit contact region can be independently accessed by selecting the word line.
The other end of each transistor may be connected in common in the semiconductor substrate to form a common source region, may be connected to a storage electrode of a memory capacitor, or may be connected to an external wiring line.
As above, four transistors connected to the common bit contact area can be accessed independently by different word lines. A semiconductor device having a high areal use factor can be realized. A semiconductor device having a novel structure can be provided.
REFERENCES:
patent: Re. 36440 (1999-12-01), Lee et al.
patent: 4651183 (1987-03-01), Lange et al.
patent: 5250831 (1993-10-01), Ishii
patent: 5298775 (1994-03-01), Ohya
patent: 5770874 (1998-06-01), Egawa
patent: 5804854 (1998-09-01), Jung et al.
patent: 5821592 (1998-10-01), Hoenigschmid et al.
patent: 6084266 (2000-07-01), Jan
patent: 065599 (1981-05-01), None
patent: 2791005 (1998-06-01), None
Armstrong Westerman Hattori McLeland & Naughton LLP
Cruz Lourdes
Fujitsu Limited
Lee Eddie C.
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