Semiconductor device with clock signal selection circuit

Details Semiconductor device with clock signal selection circuit Semiconductor device with clock signal selection circuit

2000-02-23

2003-04-15

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C713S400000

Reexamination Certificate

active

06550043

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device provided with peripheral devices such as an external memory and the like, and more particularly to a semiconductor device such as a one-chip microcomputer which is capable of varying the frequency of a clock signal to be input to a central processing unit (hereinafter referred to just as a “CPU”) so as to permit an access to the peripheral devices which are disposed in the memory device and having different access speed from one another.
2. Description of the Related Art
FIG. 10
is a block diagram showing the general configuration of a conventional semiconductor device for use in a system employing a microcomputer therein, and
FIG. 11
is a timing chart indicating the operation of the system shown in FIG.
10
. In
FIG. 10
, reference numeral
41
denotes a microcomputer, numeral
42
denotes a CPU,
43
denotes a clock signal generator,
44
denotes a wait controller,
45
denotes a peripheral device,
46
denotes a peripheral device control signal,
47
denotes a clock signal and numeral
48
denotes a ready signal.
When operating this microcomputer-application system, if a clock signal
47
having a frequency adapted to the low access speed of the peripheral device
45
is input, the overall operational speed of the entire system is lowered. For this reason, in the case where the microcomputer
41
makes an access to the peripheral device
45
, the CPU
42
is put in a waiting state as shown in
FIG. 11
, by setting the ready signal
48
which is to be input to the CPU
42
to an inactive state, so as to prolong the output period of the peripheral device control signal
46
, thereby to provide a peripheral device control signal
46
that corresponds to the low-speed access of the peripheral device
45
on the basis of the high-frequency clock signal
47
.
Since the conventional semiconductor device is configured as explained above, in accordance with a recent high-speed trend of the CPU, it has become difficult to cope with it only by use of a wait controller when accessing to a low-speed access peripheral device.
There is also another problem that the structure of a wait controller itself is so complicated that the system as a whole becomes expensive.
Further, since the operational clock frequency of the CPU is not changed but maintained at high level during the accessing operation to a low-speed access peripheral device, there has been a waste of power consumption.
Still further, since there is a difference in accessing speed among individual peripheral devices, it is difficult to provide a clock signal of a frequency adapted to each of the target peripheral devices.
SUMMARY OF THE INVENTION
The present invention has been proposed to solve the problems aforementioned, and it is an object of the present invention to provide a semiconductor device which is capable of varying the frequency of a clock signal to be input to the CPU, in accordance with the peripheral device to be accessed, but without using the wait controller.
Another object of the present invention is to provide a semiconductor device that provides a clock signal corresponding to the frequency of the peripheral device to be accessed.
The semiconductor device according to a first aspect of the present invention is constructed in such a manner that it comprises: a CPU, an address decoder that decodes an address signal transmitted from the CPU and outputs an address area specifying signal for specifying an address area in which a designated address is included, a frequency divider that divides a base clock signal and outputs one or more than one low-speed clock signals whose frequencies have been lowered, and a clock signal decision circuit that selects as to which one of the base clock signal and the frequency-divided clock signals is to be input to the CPU in accordance with the address area specifying signal output from the address decoder.
The semiconductor device according to another aspect of the present invention further comprises a clock specifying register composed of a plurality of clock specifying bits, into which data can be written by the CPU, and each corresponding to the respective one of a predetermined number of divided address areas, wherein each of the clock specifying bits instructs to the clock signal decision circuit as to which one of the base clock signal and the frequency-divided clock signals is to be input to the CPU.
The semiconductor device according to further aspect of the present invention further comprises a frequency specifying register composed of a plurality of frequency specifying bits, into which data can be written by the CPU, each corresponding to the respective one of a plurality of stages in a multi-stage frequency divider, wherein each of the frequency specifying bits instructs to the clock signal decision circuit as to which one of the clock signals is to be input to the CPU, the division rates of which clock signals being different from one another obtainable from each of the multi-stage frequency divider composed of a plurality of flip-flops.
The semiconductor device according to still further aspect of the present invention further comprises: a clock specifying register composed of a plurality of clock specifying bits, into which data can be written by the CPU, and each corresponding to the respective one of a predetermined number of divided address areas, wherein each of the clock specifying bits instructs to the clock signal decision circuit as to which one of the base clock signal and the frequency-divided clock signals is to be input to the CPU, and a frequency specifying register composed of a plurality of frequency specifying bits, into which data can be written by the CPU, each corresponding to the respective one of a plurality of stages in a multi-stage frequency divider, wherein each of the frequency specifying bits instructs to the clock signal decision circuit as to which one of the clock signals is to be input to the CPU, the division rates of which clock signals being different from one another obtainable from each of the multi-stage frequency divider composed of a plurality of flip-flops.
The semiconductor device as constructed above can be arranged such that it further comprises a disable register, into which data can be written by the CPU, and a logic circuit connected to the disable register, wherein when a predetermined value is written into the disable register, the function of the clock signal decision circuit is disabled, and a base clock signal can be always input to the CPU.


REFERENCES:
patent: 5125088 (1992-06-01), Culley
patent: 5497263 (1996-03-01), Masuda et al.
patent: 5581746 (1996-12-01), Watanabe
patent: 5809336 (1998-09-01), Moore et al.
patent: 2-47743 (1990-02-01), None

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