Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-05-03
2011-05-03
Landau, Matthew C (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257SE29266, C257SE21435, C438S163000, C438S290000, C438S299000, C438S339000
Reexamination Certificate
active
07936006
ABSTRACT:
An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as the source and drain extensions.
REFERENCES:
patent: 4894694 (1990-01-01), Cham et al.
patent: 4985744 (1991-01-01), Spratt et al.
patent: 5650340 (1997-07-01), Burr et al.
patent: 5696012 (1997-12-01), Son
patent: 5854509 (1998-12-01), Kunikiyo
patent: 5989986 (1999-11-01), Hsieh
patent: 5989992 (1999-11-01), Yabu et al.
patent: 6075262 (2000-06-01), Moriuchi et al.
patent: 6157064 (2000-12-01), Huang
patent: 6177319 (2001-01-01), Chen
patent: 6262445 (2001-07-01), Swanson et al.
patent: 6287988 (2001-09-01), Nagamine et al.
patent: 6306712 (2001-10-01), Rodder et al.
patent: 6399973 (2002-06-01), Roberds
patent: 6541343 (2003-04-01), Murthy et al.
patent: 6563152 (2003-05-01), Roberds et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6713360 (2004-03-01), Jain et al.
patent: 6743684 (2004-06-01), Liu
patent: 6870179 (2005-03-01), Shaheed et al.
patent: 6906393 (2005-06-01), Sayama et al.
patent: 6939814 (2005-09-01), Chan et al.
patent: 6995430 (2006-02-01), Langdo et al.
patent: 7022561 (2006-04-01), Huang et al.
patent: 7052964 (2006-05-01), Yeo et al.
patent: 7053400 (2006-05-01), Sun et al.
patent: 7132704 (2006-11-01), Grudowski
patent: 7138309 (2006-11-01), Lee et al.
patent: 7193254 (2007-03-01), Chan et al.
patent: 7208362 (2007-04-01), Chidambaram
patent: 7256084 (2007-08-01), Lim et al.
patent: 7259105 (2007-08-01), Kim
patent: 7265419 (2007-09-01), Minami
patent: 7288448 (2007-10-01), Orlowski et al.
patent: 7314793 (2008-01-01), Frohberg et al.
patent: 7423283 (2008-09-01), Luo et al.
patent: 7429775 (2008-09-01), Nayak et al.
patent: 7528028 (2009-05-01), Liang et al.
patent: 2005/0040460 (2005-02-01), Chidambarrao et al.
patent: 2005/0136606 (2005-06-01), Rulke et al.
patent: 2005/0247986 (2005-11-01), Ko et al.
patent: 2005/0260817 (2005-11-01), Kim
patent: 2005/0285187 (2005-12-01), Bryant et al.
patent: 2006/0009041 (2006-01-01), Iyer et al.
patent: 2006/0014350 (2006-01-01), Wang et al.
patent: 2006/0189167 (2006-08-01), Wang et al.
patent: 2006/0244074 (2006-11-01), Chen et al.
patent: 2006/0267106 (2006-11-01), Chao et al.
patent: 2007/0001217 (2007-01-01), Chen et al.
patent: 2007/0004123 (2007-01-01), Bohr et al.
patent: 2007/0010073 (2007-01-01), Chen et al.
patent: 2007/0034963 (2007-02-01), Sudo
Yuhao Luo, et al., “Strain-silicon CMOS Using Etch-stop Layer And Method Of Manufacture”, U.S. Appl. No. 11/146,640, filed Jun. 7, 2005, 17 pages, available from Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124.
Deepak Kumar Nayak, et al, “CMOS Device With Stressed Sidewall Spacers”, U.S. Appl. No. 11/221,507, filed Sep. 8, 2005, 13 pages, available from Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/146,640, filed Jun. 7, 2005, Luo et al.
U.S. Appl. No. 11/221,507, filed Sep. 8, 2005, Nayak et al.
T. Ghani et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, IEEE, 2003, pp. 1-3, available from tahr.ghani@intel.com, or Intel Corporation (Santa Clara) Corporate Office, 2200 Mission College Blvd., Santa Clara, California 95052-8119.
Min Chin Chai, “90 nm Node CMOS Technology Comparison between Intel Corporation and Samsung Electronics”, pp. 1-6, May 8, 2003 available from Intel Corporation (Santa Clara) Corporate Office, 2200 Mission College Blvd., Santa Clara, California 95052-8119.
B. P. R. Chidambaram et al., “35% Drive Current Imporvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS”, 2004 Sumposium on VLSI Technology Digest of Technical Papers, pp. 48-49, available from Texas Instruments, MS 3739, 13560 N. Central-Expressway, Dallas, TX 75243.
Pidin, S. et al., “A Novel Strain Enhanced CMOS Architecture Using Selectively Deposited High Tensile and High Compressive Silicon Nitride Films”, IEEE 2004, pp. 1-8, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Thompson, S. et al.,“A 90 nm Logic Technology Featuring 50 nm Strained Silicon Channel Transistors, 7 Layers of Cu Interconnects, Low K ILD, and 1 um2 SRAM Cell”, iedm 2002, pp. 1-32, available from Intel Corporation, www.intel.com/research/silicon.
Luo, Y. et al., “Enhancement of CMOS Performance by Process-Induced Stress”, IEEE Transactions on Seminconductors Manufacturing, vol. 18, No. 1, Feb. 2005, pp. 63-68.
U.S. Appl. No. 11/146,640, Luo, Y. et al. “Strain-Silicon CMOS using Etch-Stop Layer and Method of Manufacture”, filed Jun. 7, 2005, Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/221,507, Nayak, D.K. et al., “CMOS Device With Stressed Sidewall Spacers”, filed Sep. 8, 2005, Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/095,814, Nayak et al.,“Method of Fabricating Strain-Silicon CMOS”, filed Mar. 31, 2005, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
Brand, A. et al., “Intel's 0.25 Micron, 2.0Volts Logic Process Technology”, pp. 1-9, available from Intel Corporation (Santa Clara) Corporate Office, 2200 Mission College Blvd., Santa Clara, California 95052-8119, Intel Technology Journal Q3'98 (Third Quarter 1998).
U.S. Appl. No. 12/200,851, filed Aug. 28, 2008, Luo et al. Xilinx, Inc. 2100 Logic Drive, San Jose, California.
U.S. Appl. No. 12/200,871, filed Aug. 28, 2008, Nayak et al., Xilinx, Inc. 2100 Logic Drive, San Jose, California.
Gitlin Daniel
Luo Yuhao
Nayak Deepak Kumar
George Thomas
Hewett Scott
Landau Matthew C
Snow Collen E
Xilinx , Inc.
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