Static information storage and retrieval – Read/write circuit – Testing
Patent
1991-12-23
1993-08-10
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Testing
36523006, G11C 2900
Patent
active
052355497
ABSTRACT:
A memory device having test circuitry incorporated into its design to enable direct external access to the bit lines of a single cell is described. When the device is put in test mode by applying external control signals, peripheral I/O circuitry is disabled. Once the I/O circuitry is disabled the test circuitry selects and enables the section of the array in which the selected cell is located through transfer circuits. The enabled transfer circuit for the selected section couples data between the selected cell and a set of predetermined I/O terminals.
REFERENCES:
patent: 4899313 (1990-02-01), Kumanoya
patent: 4914632 (1990-04-01), Fujishima
patent: 4958324 (1990-09-01), Devin
patent: 4992985 (1991-02-01), Miyazawa
patent: 5060198 (1991-10-01), Kowalski
patent: 5111433 (1992-05-01), Miyamoto
patent: 5134586 (1992-07-01), Steele
patent: 5151881 (1992-09-01), Kajigaya
Sarangi Ananda G.
Young Ian A.
Intel Corporation
LaRoche Eugene R.
Zarabian A.
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