Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
1998-06-12
2001-04-03
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S676000, C257S735000, C438S118000
Reexamination Certificate
active
06211573
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device with an improved lead-hip adhesion structure and a lead frame, and more particularly to a semiconductor device with a lead-on-chip structure and a lead frame to be used therefor.
FIG. 1
is a fragmentary cross sectional elevation view illustrative of a conventional lead-on-chip structure of a semiconductor device. Inner leads
1
extend over a top surface of a semiconductor chip
4
. The inner leads
1
have stitch portions
2
at inside edges thereof. An insulative adhesive tape
3
is adhered with bottom surfaces of the stitch portions
2
of the inner leads
1
aligned in the left side. Another insulative adhesive tape
3
is adhered with bottom surfaces of the stitch portions
2
of the inner leads
1
aligned in the right side. Each of the insulative adhesive tapes
3
has both surfaces on which an insulative adhesive agent has been applied. Alternatively, each of the insulative adhesive tapes
3
has both surfaces on which adhesive layers have been formed. The inner leads
1
extend toward a center line of the semiconductor chip
4
. The semiconductor chip
4
is bonded or adhered with the bottom surfaces of the insulative adhesive tapes
3
, wherein the insulative adhesive tapes
3
have already been adhered to the bottom surfaces of the stitch portions
2
of the inner leads
1
. The semiconductor chip
4
has two alignments of bonding pads
10
along the center line so that individual bonding pads correspond to individual inner leads
1
as illustrated in FIG.
2
. The two alignments of bonding pads
10
of the semiconductor chip
4
are positioned inside of the stitch portions
2
of the inner leads
1
and also the insulative adhesive tapes
3
. The stitch portion
2
of the inner lead
1
is bonded through a bonding wire
5
to the corresponding bonding pad
10
formed on the semiconductor chip
4
so that the inner leads
1
are electrically connected through the bonding wires
5
to the corresponding bonding pads
10
formed on the semiconductor chip
4
.
FIG. 3
is a fragmentary cross sectional elevation view illustrative of the above conventional lead-on-chip structure of the semiconductor device, wherein inner leads are in contact with edges of the semiconductor chip
4
to describe a first problem with the above conventional lead-on-chip structure. As shown in
FIG. 3
, the inner leads
1
are fixed at the stitch portions
2
by the insulative adhesive tapes
3
but other portions of the inner leads
1
positioned outside of the stitch portions
2
are not fixed. The semiconductor chip
4
is mounted on a printed circuit board by use of a sealing resin wherein a heat is applied to the semiconductor chip
4
and the inner leads
1
. The insulative adhesive tapes
3
have a different thermal expansion coefficient from that of the sealing resin, for which reason a stress is generated by the difference in thermal expansion coefficient between the insulative adhesive tapes
3
and the sealing resin. The stress is applied between the insulative adhesive tapes
3
and the sealing resin, whereby a pealing may be generated between the insulative adhesive tapes
3
and the sealing resin. In order to avoid this problem with pealing between the insulative adhesive tapes
3
and the scaling resin, it is effective to narrow the width of the insulative adhesive tapes
3
as much as possible. In the above viewpoints, it is preferable that a pair of possible slender insulative adhesive tapes
3
are provided so that when the semiconductor chip
4
has been bonded to the bottom surfaces of the insulative adhesive tapes
3
, the possible slender insulative adhesive tapes
3
are positioned along the two alignments of the bonding pads
10
formed on the semiconductor chip
4
as closely to the two alignments of the bonding pads
10
, so as to shorten the length of the individual bonding wires
10
. The long bonding wires have a problem with unstability in shape thereof and also is likely to be deformed by a flow of molten sealing resin when the sealing resin is injected tbereunto. For those reasons, it is preferable to shorten the length of the bonding wire
10
. This requires that the stitch portion
2
of the inner lead
1
is positioned as closely to the bonding pad
10
provided close to the center line of the semiconductor chip
4
as possible. This results in that a long part of the inner lead
1
positioned outside of the stitch portion
2
extends over the semiconductor chip
4
. This is remarkable as the size of the semiconductor chip
4
becomes large. The long part of the inner lead
1
positioned outside of the stitch portion
2
is not fixed by the insulative adhesive tapes
3
. Namely, the long inner lead
1
extending over the semiconductor chip
4
is fixed only at the stitch portion
2
thereof by the slender insulative adhesive tape
3
. For those reasons, even if a slight deformation appears to such the inner lead
1
when the scaling resin is injected, the inner lead
1
might be made into contact with the edge of the semiconductor chip
4
. The likelihood of contact between the inner lead
1
and the edge of the semiconductor chip
4
is high as the size of the semiconductor chip
4
is large.
The above conventional lead-on-chip structure of the semiconductor device is further engaged with a second problem with likelihood of exposure of the tops of the bonding wires
5
or the bottom surface of the semiconductor chip
4
from the sealing resin even after the semiconductor device has been packaged with the sealing resin. As described above, the long part of the individual inner lead
1
extends over the semiconductor chip
4
and is not fixed by the slender insulative adhesive tape
3
. This allows the semiconductor chip
4
to move or displace in a direction vertical to the surface of the semiconductor chip
4
by the pressure of the sealing resin injected into dies for molding the semiconductor device.
FIG. 4A
is a fragmentary cross sectional elevation view illustrative of a semiconductor package, wherein the semiconductor chip
4
has been moved upwardly by the pressure of the sealing resin injected into the dies and the tops of the bonding wires
5
are shown from the sealing resin.
FIG. 4B
is a fragmentary cross sectional elevation view illustrative of a semiconductor package, wherein the semiconductor chip
4
has been moved downwardly by the pressure of the sealing resin injected into the dies and the bottom surface of the semiconductor chip
4
is shown from the sealing resin. Once either the top of the bonding wire
5
or the bottom of the semiconductor chip
4
is exposed from the sealing resin as illustrated in
FIG. 4A
or
4
B, then a reliability of packaging is remarkably deteriorated and it may no longer be possible to use such the semiconductor package. Namely, the above conventional lead-on-chip structure may result in remarkable drop of the yield of the products.
In order to avoid the above problem with movement of the semiconductor chip
4
by pressure of the molten resin injected into the dies, it is required to select an optimum condition for injection of the resin into the dies. Actually, however, the available ranges of the condition for the injection such as injection speed are extremely narrow. Determination of the available ranges of the condition for the injection is time consuming and complicated procedures. Further, the available ranges of the condition for the injection are changed even by a slight variation in lot of the resin. This means it required to newly set or determine the optimum condition or extremely narrow available range even when the lot of the resin is changed.
The above lead-on-chip structure is also engaged with the following third problem. Even if the tops of the bonding wires
5
or the bottom of the semiconductor chip
4
are not exposed from the sealing resin, movement or shift in vertical direction to the surface of the semiconductor chip
4
results in variation in thickness of the resin from predetermined thicknesses.
Chaudhuri Olik
NEC Corporation
Weiss Howard
Young & Thompson
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