Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-10
2001-09-18
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S342000
Reexamination Certificate
active
06291856
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device, such as an insulated gate metal oxide semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a bipolar transistor and a diode, which has a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state.
BACKGROUND OF THE INVENTION
A high-resistance layer between two electrodes provided on opposite two principal faces must be thick in order to achieve the high withstand voltage in a longitudinal semiconductor device, in which an electric current flows between the two electrodes. A device having the thick high-resistance layer provides high ON-state resistance between the two electrodes, and thus, the loss is unavoidably increased. In short, there is a trade-off relationship between the ON-state resistance (the current-carrying capacity) and the withstand voltage. As is well known, the trade-off relationship applies to a variety of semiconductor devices such as an IGBT, a bipolar transistor and a diode. The problem also applies to a lateral semiconductor device in that a direction in which a drift current flows in the ON state is different from a direction in which a depletion layer spreads due to the reverse bias in the OFF state.
To address the above-mentioned problem, European Patent No. 0,053,854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, and Japanese Patent Provisional Publication No. 9-266311 developed by the inventors of this invention have disclosed a semiconductor device having a drift layer composed of a parallel pn layer, in which n regions and p regions with high impurity density are alternately piled up. In this semiconductor device, the parallel pn layer is depleted in the OFF state to burden the withstand voltage.
In the following description, a semiconductor device having a drift layer composed of a parallel pn layer, which conducts electricity in the ON state and is depleted in the OFF state, will be referred to as a super-junction semiconductor device.
The above-mentioned conventional semiconductor device is in an experimental stage, and it is still impossible to manufacture the devices in large quantities. For example, the impurity density and width of the parallel pn layer need to be uniform, but actually, the impurity density and the width are always uneven in the manufacturing process.
Moreover, no specific numerical value has been specified with respect to an L load avalanche breakdown current, which is an important factor in the manufacture of the devices. The L load avalanche breakdown current is preferably more than a rated current in order to manufacture the devices.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention to provide a super-junction semiconductor device, which significantly improves the trade-off relation between the ON-resistance and the withstand voltage, achieves a high withstand voltage by specifying the allowable range of the impurity density, width, or the like and is suitable for the mass production.
To achieve the above-mentioned object, the present invention is directed to a super-junction semiconductor device, which comprises first and second principal faces, two principal electrodes provided on the principal faces, and a parallel pn layer, in which first-conductivity-type drift regions and second-conductivity-type partition regions are arranged alternately, the parallel pn layer being provided between the two principal electrodes and conducting electricity in the ON state and being depleted in the OFF state, wherein the quantity of impurities in the first-conductivity-type drift regions is within the range between 100% and 150% of the quantity of impurities in the second-conductivity-type partition regions.
Particularly, the quantity of impurities in the first-conductivity-type drift regions is preferably between 110% and 150% of the quantity of impurities in the second-conductivity-type partition regions.
The first-conductivity-type drift regions and the second-conductivity-type partition regions are preferably arranged in stripes with the same width.
The present invention is also directed to a super-junction semiconductor device, which comprises first and second principal faces, two principal electrodes provided on the principal faces, and a parallel pn layer, in which first-conductivity-type drift regions and second-conductivity-type partition regions are arranged alternately, the parallel pn layer being provided between the two principal electrodes and conducting electricity in the ON state and being depleted in the OFF state, wherein the first-conductivity-type drift regions and the second-conductivity-type partition regions have almost the same width and are arranged in stripes, and the quantity of impurities in either one of the first-conductivity-type drift regions and the second-conductivity-type partition regions is within the range between 92% and 108% of the quantity of impurities in the other regions.
Particularly, the average impurity density of either one of the conductive drift regions and the second-conductivity-type partition regions may be within the range between 92% and 108% of the average impurity density of the other regions. The impurity density of either one of the conductive drift regions and the second-conductivity-type partition regions may be within the range between 92% and 108% of the impurity density of the other regions.
The width of either one of the conductive drift regions and the second-conductivity-type partition regions is within the range between 94% and 106% of the width of the other regions.
The first-conductivity-type drift regions and the second-conductivity-type partition regions have substantially the same quantity of impurities in order to deplete the parallel pn layer, in which the first-conductivity-type drift regions and the second-conductivity-type partition regions are arranged alternately, in the OFF state. If the impurity density of either one of the first-conductivity-type drift regions and the second-conductivity-type partition regions is half the impurity density in the other regions, the one regions must be twice as wide as the other regions. Therefore, if the first-conductivity-type drift regions and the second-conductivity-type partition regions have the same impurity density, they can be formed in the same width. This is preferable in order to utilize the surface of the semiconductor efficiently.
The first-conductivity-type drift regions and the second-conductivity-type partition regions with the same impurity density and width can be depleted almost uniformly. This keeps the decrease in the withstand voltage, which results from the incomplete depletion, at about 10%.
In order to manufacture the super-junction semiconductor device, either one of the conductive drift regions and the second-conductivity-type partition regions with the impurities in the quantity within the range between 92% and 108% of the quantity of impurities in the other regions may be formed by an epitaxial growth. Alternatively, the impurities in quantity within the range between 92% and 108% of the quantity of impurities required for forming either one of the first-conductivity-type drift regions and the second-conductivity-type partition regions are implanted, and the other regions are then formed by thermal diffusion.
REFERENCES:
patent: 5216275 (1993-06-01), Chen
patent: 5438215 (1995-08-01), Tihanyi
patent: 6081009 (2000-07-01), Neilson
patent: 6097063 (2000-08-01), Fujihira
patent: 6184555 (2001-02-01), Tihanyi et al.
patent: 0053854 (1986-02-01), None
Tatsuhiko Fujihira, “Theory of Semiconductor Superjunction Devices”, Oct. 1997, pp. 6254-6262, Jpn. J. Appl. Phys. vol. 36 (1997), Part 1, No. 10.
Fujihira Tatsuhiko
Iwamoto Susumu
Miyasaka Yasushi
Ohnishi Yasuhiko
Ueno Katsunori
Fuji Electric & Co., Ltd.
Ngo Ngan V.
Rossi & Associates
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