Semiconductor device with a reduced width gate dielectric and me

Details Semiconductor device with a reduced width gate dielectric and me Semiconductor device with a reduced width gate dielectric and me

1998-09-08

2000-10-03

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438591, 438619, 438287, 257410, 257411, H01L 213205, H01L 214763

Patent

active

061272515

ABSTRACT:
The present invention is directed to a semiconductor device having a reduced feature size and a method of making same. The device is comprised of a gate dielectric positioned above a semiconducting substrate, and a gate conductor positioned above said gate dielectric. The width of the gate dielectric being less than the width of the gate conductor. The device further comprises a plurality of sidewall spacers adjacent said conductor. The method is comprised of forming a gate dielectric above the surface of a semiconducting substrate, forming a gate conductor above the gate dielectric, and wet etching the gate dielectric to a finished width that is less than the width of the gate conductor.

REFERENCES:
patent: 5717222 (1998-02-01), Nakamura et al.
patent: 5766998 (1998-06-01), Tseng
patent: 5864160 (1999-01-01), Buynoski
patent: 5900668 (1999-05-01), Wollesen
J. L. Vossen and W Kern, eds. Thin Film Processes, Academic Press: New York, pp. 413-424, 1978.
S. Wolf, Silicon Processing for the VSLI Era, vol. 2: Process Integration, pp. 435-436, 1990.
H. S. Momose, et al. "High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs" Electron Devices Meeting, IEEE, pp. 105-108, Dec. 1996.

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