Semiconductor device with a line and method of fabrication...

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

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C438S622000, C438S637000, C438S638000, C438S696000

Reexamination Certificate

active

11148307

ABSTRACT:
A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

REFERENCES:
patent: 6613664 (2003-09-01), Barth et al.
patent: 2002/0109234 (2002-08-01), Park et al.
patent: 2003/0087520 (2003-05-01), Chen et al.
patent: 2003/0100181 (2003-05-01), Park et al.
patent: 2003/0160331 (2003-08-01), Fujisawa
patent: 7-14836 (1995-01-01), None
patent: 2000-114261 (2000-04-01), None
patent: 2000-133711 (2000-05-01), None
patent: 2001-77195 (2001-03-01), None
patent: 2002-64138 (2002-02-01), None
T.J. Dalton, et al., “A 90nm Dual Damascene Hybrid (Organic/Inorganic) Low-k-Copper BEOL Intergration Scheme”, Advanced Metallization Conference 2003, Materials Research Society, 2004, pp. 85-89.

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