Static information storage and retrieval – Read/write circuit – Complementing/balancing
Reexamination Certificate
2005-11-15
2005-11-15
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Complementing/balancing
C365S230060, C365S189050
Reexamination Certificate
active
06965533
ABSTRACT:
A write operation of a MRAM in which a current necessary for inverting magnetization of an MTJ element has to be passed through a data line and therefore current consumption is large. The write operation comprises: comparing input data DI with read data GO read from a memory cell array and encoding the input data DI to form write data GI by a data encoder WC; and decoding the read data GO by a data decoder RD to form output data DO. In a nonvolatile semiconductor memory in which the current is passed through the data line to write data into a memory cell, the number of bits to be written during the write operation is reduced, and the current consumption can be reduced. This can realize the MRAM including a low-power highly-integrated memory.
REFERENCES:
patent: 5793685 (1998-08-01), Suma
patent: 5954435 (1999-09-01), Yoshida
patent: 6094368 (2000-07-01), Ching
patent: 6209113 (2001-03-01), Roohparvar
patent: 6272066 (2001-08-01), Ooishi
patent: 6275084 (2001-08-01), McAdams
patent: 7-220479 (1994-02-01), None
patent: 9-63286 (1995-08-01), None
patent: 2002-93158 (2000-09-01), None
Roy Scheuerlein, William Gallagher, Stuart Parkin, Alex Lee, Sam Ray, Ray Robertazzi and WilliamReohr, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell”, 2000 IEEE International Solid-State Circuits Conference, 1 page.
Manzur Gill, Tyler Lowrey and John Park, “Ovonic Unified Memory—A High-Performance Nonvolatile Memory Technology for Stand-Alone Memory and Embedded Applications”, ISSCC 2002/Feb. 5, 2002/Session 12/TD: Digital Directions/12.4, 2 pages.
Mircea R. Stan and Wayne P. Burleson, “Bus-Invert Coding for Low-Power I/O”, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 3, No. 1, Mar. 1995, pp. 49-58.
M. Durlam, P. Naji, A. Omair, M.DeHerrera, J. Calder, J.M. Slaughter, B. Engel, N. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. Kyler, J. Ren, J. Molia, B. Feil, R. Williams, and S. Tehrani, “A Low Power 1Mbit MRAM Based on ITIMTJ Bit Cell Integrated with Copper Interconnects”, IEEE 2002 Symposium on VLSI Circuits Digest of Technical Papers, pp. 158-161.
Matsuoka Hideyuki
Sakata Takeshi
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Hitachi , Ltd.
Nguyen Tuan T.
Phung Anh
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