Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2001-01-25
2003-09-09
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C438S401000, C438S462000
Reexamination Certificate
active
06617702
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit (IC) design. In particular, it relates to a method and apparatus globally aligning the front and back sides of a substrate. Specifically, it relates to a method and apparatus globally aligning the front and back sides of a substrate to provide for wireless communications between circuit systems fabricated on or bonded to the substrate.
BACKGROUND OF THE INVENTION
It is understood that in order to achieve advanced computing systems, the integration of high-density digital, rf, optical, and memory components fabricated on different substrates needs to be realized. Problems arise in the interconnection of multiple substrates with specialized functionality with other substrates, and in the spatial registration of multiple substrates for localized optical interconnect of the multiple substrates. Several challenges in the packaging of high speed opto-electronic components must also be met, such as low cost, small package size, and high data rates.
The most difficult problems in interconnecting substrates are those associated with the transmitter and receiver modules, which require high precision laser fiber and detector fiber alignment to achieve high transfer to and from the fiber, respectively. Laser fiber alignment demands particularly stringent tolerances, and hence, adds appreciable cost to laser fiber module packaging.
Conventionally, a laser fiber module is fabricated first by fixing the laser chip to a suitable substrate, followed by activation of the laser. A fiber which is securely fastened to a suitable carrier is then positioned near the laser, and is moved in a search pattern until the maximum light power is coupled into it, as indicated by a detector placed at the far end of the fiber. The fiber is then secured to the substrate. This procedure is termed active alignment.
Active alignment is time consuming and relatively difficult; it increases the cost. Another approach with the promise of lower packaging cost is to avoid activating the laser. It is called passive alignment. A typical passive alignment technique is the flip chip solder bump technique. In this technique, solder-wettable pads are provided on the two surfaces to be bonded, with each pad on one of the surface being covered by the solder. It has been documented that solder bump flip chip assembly of LED has important advantages over traditional epoxy die attachment and wire bonding. The self-aligning feature of the solder bump reflow process have been demonstrated to result in an array alignment accuracy of one micron in both X and Y directions.
Typically, the preferred technique from the above-described alignment techniques is the passive flip chip solder bump technique. However, even with the solder bump technique, while in-plane positional accuracy can be realized, vertical positional accuracy, which relies on the control of the thickness of the deposited solder, cannot always be realized; since, vertical positional accuracy depends on the application.
The laser application technique is the most difficult. This is due to the more demanding positional accuracy required and the relatively small surface area of the laser chip does not permit the large number of large diameter solder bumps which guarantee reproducible precision in other applications. In light of these challenges, novel alignment methods are needed which overcome the difficulties and challenges of prior art alignment techniques.
SUMMARY
An aspect of the present invention is to provide a method and apparatus globally aligning circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates, where the method overcomes the disadvantages of prior art alignment techniques.
In accordance with the above aspect of the present invention, the present disclosure provides several embodiments of alignment methods and packages formed for globally aligning and providing wireless communications between circuit systems fabricated on or bonded to one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate.
In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates.
Still, in another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.
REFERENCES:
patent: 5200631 (1993-04-01), Austin et al.
patent: 6052498 (2000-04-01), Paniccia
patent: 8-861133 (1998-12-01), None
Hsu Louis L.
Joshi Rajiv V.
Mandelman Jack A.
Radens Carl
Yuan Tsorng-Dih
Chambliss Alonzo
Dilworth & Barrese LLP
IBM Corporation
Talbott David L.
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