Semiconductor device using SiGe for substrate

Details Semiconductor device using SiGe for substrate Semiconductor device using SiGe for substrate

2007-01-04

2010-10-19

Bryant, Kiesha R (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S371000, C257SE29255, C257SE29270, C257SE27067, C438S300000

Reexamination Certificate

active

07816739

ABSTRACT:
A semiconductor device includes a first semiconductor layer, an n-type/p-type second semiconductor layer, p-type
-type third semiconductor layers and a first gate electrode. The second semiconductor layer is formed on the first semiconductor layer and has an oxidation rate which is lower than that of the first semiconductor layer. The third semiconductor layers are formed in the second semiconductor layer and have a depth reaching an inner part of the first semiconductor layer. In case that the second and third semiconductor layers are n-type and p-type, respectively, a lattice constant of the second semiconductor layer is less than that of the third semiconductor layer. In case that the second and third semiconductor layers are p-type and n-type, respectively, the lattice constant of the second semiconductor layer is greater than that of the third semiconductor layer. A first gate electrode is formed on the second semiconductor layer.

REFERENCES:
patent: 6593641 (2003-07-01), Fitzergald
patent: 6621131 (2003-09-01), Murthy et al.
patent: 2005/0133819 (2005-06-01), Kawasaki
patent: 2002-237590 (2002-08-01), None
patent: 2004-200335 (2004-07-01), None
patent: 2005-142431 (2005-06-01), None
T. Ghani, et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” Portland Technology Development, 3 pages, 2003.

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