Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-11-09
2001-07-31
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S639000, C438S672000
Reexamination Certificate
active
06268280
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the cell structure of a dynamic RAM (DRAM), for example, and more particularly to an STC (Stacked Capacitor) type semiconductor memory device in which memory cell capacitors are formed in self-alignment with bit lines above the bit lines and a method for manufacturing the same.
Recently, semiconductor memory devices, particularly DRAMs are miniaturized, the resolution in the lithography technology is markedly enhanced and the line width and the interval between the lines are progressively reduced. However, the improvement of the alignment technique cannot catch up with the development of the resolution and it becomes more important to take effective measures for preventing occurrence of alignment error.
As one of the measures for preventing occurrence of alignment error, for example, there is provided a technique disclosed in “C. W. Kaanta et al. ‘Dual Damascene:A ULSI Wiring Technology’, VMIC, pp. 144 to 152, 1991” in the technology for forming contact holes and wires in a borderless manner. Further, as a device obtained by applying this technique to bit line contacts and bit lines, there is provided a memory cell described in “D. Kenny et al. ‘A Buried-Plate Trench Cell for 64-Mb DRAM’, VLSI Tech. Symp. pp. 14 to 15, 1992”.
Further, in a cell using an STC capacitor, as the technique for forming memory cell capacitors in self-alignment with bit lines, for example, there is proposed a memory cell described in “M. Fukumoto et al, ‘Stacked capacitor cell technology for
16
M DRAM using double self-aligned contacts’, ESSDERC 90, pp. 461 to 464, 1990”.
The Dual Damascene technology is explained with reference to FIG.
1
.
First, as shown in
FIG. 1A
, an inter-level insulating film
102
whose upper surface portion is planarized is formed on a lower-level interconnection
101
. Then, a first resist
104
having a contact hole pattern
103
and a second resist
106
having an upper-level interconnection pattern
105
are formed on the upper-level insulating film
102
. Next, as shown in
FIG. 1B
, the inter-level insulating film
102
is selectively etched to form a contact hole
107
with the resists
104
,
106
used as a mask. After this, as shown in
FIG. 1C
, an exposed part of the first resist
104
is removed to form an upper-level interconnection pattern
108
. At this time, the surface portion of the second resist
106
is also removed by an amount corresponding to the film thickness of the first resist
104
. Then, as shown in
FIG. 1D
, the inter-level insulating film
102
is selectively etched to form a contact hole
109
and an upper-level interconnection pattern
110
. Next, as shown in
FIG. 1E
, a metal film
111
is deposited on the semiconductor structure to completely fill the contact hole
109
and the upper-level interconnection pattern
110
. Then, as shown in
FIG. 1F
, the metal film
111
is etched back by use of a CMP (Chemical Mechanical Polishing) method to form an upper-level interconnection
112
and make the upper surface of the structure flat.
When the Dual Damascene technology is applied to a cell using an STC type capacitor, there occurs a problem that the memory capacitor cannot be formed in self-alignment with the bit line.
That is, in order to form a memory capacitor, it is necessary to form a self-aligned contact hole in the inter-level insulating film to reach the surface of a source or drain diffusion layer formed on the semiconductor substrate. However, since the surface of the upper-level interconnection
112
is exposed, the upper-level interconnection
112
will be exposed when the inter-level insulating film
102
is etched to form the contact hole. In order to solve the above problem, it is necessary to previously form an insulating film
113
used as an etching mask on the upper-level interconnection and then form a contact hole
114
as shown in FIG.
2
. However, in this case, it becomes impossible to form the contact hole in a self-alignment manner. Therefore, the contact hole must be formed at a preset distance from the upper-level interconnection
112
to provide a sufficient alignment tolerance, and as a result, the interval between the interconnections becomes large, thereby making it difficult to attain fine patterning.
BRIEF SUMMARY OF THE INVENTION
Accordingly, an object of this invention is to provide a semiconductor device having contact holes formed in self-alignment with bit lines and a method for manufacturing the same.
According to one aspect of this invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of forming a first insulating film on a semiconductor substrate; forming trenches in the first insulating film; filling conductive films in the trenches; etching the conductive films by a preset thickness in the depth direction thereof to form stepped portions which have a difference in level with respect to the first insulating film; and filling second insulating films in the stepped portions.
According to another aspect of this invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of forming a first insulating film on a semiconductor substrate; forming trenches in the first insulating film; filling conductive films in the trenches; etching the conductive films by a preset thickness in the depth direction thereof to form stepped portions which have a difference in level with respect to the first insulating film; filling second insulating films in the stepped portions; and etching the first insulating film by the selective etching process using the second insulating films as a mask to form contact holes adjacent to the trenches.
According to still another aspect of this invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of forming a first insulating film on a semiconductor substrate; forming trenches in the first insulating film; forming conductive films on the inner walls of the trenches; filling second conductive films in the trenches; etching the second conductive films by a preset thickness in the depth direction thereof and etching the first conductive films by an amount larger than the etching amount-of the second conductive film to form stepped portions which have a difference in level with respect to the first insulating film; and filling second insulating films in the stepped portions.
According to another aspect of this invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of forming a first insulating film on a semiconductor substrate; forming trenches in the first insulating film; filling conductive films in the trenches to form bit lines; etching the conductive films by a preset thickness in the depth direction thereof to form stepped portions which have a difference in level with respect to the first insulating film; filling second insulating films in the stepped portions; and etching the first insulating film by the selective etching process using the second insulating films as a mask to form storage node contact holes adjacent to the trenches.
According to another aspect of this invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of forming an element isolation insulating film on a semiconductor substrate; forming MOSFETs by forming gate electrodes over the semiconductor substrate with gate insulating films disposed therebetween and selectively doping impurity into the semiconductor substrate to form source and drain diffusion regions; forming a first insulating film to cover the MOSFETs; forming bit line contact holes in the first insulating film; forming trenches in which bit lines are formed in the later step in the first insulating film; filling conductive films in the trenches and bit line contact holes to form bit lines which are each electrically connected to one of the source and drain diffusion regions of a corresponding one of the MOSFETs; etching the conductive films by a preset thickness in the depth di
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Wilczewski Mary
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