Semiconductor device using diode place-holders and method of...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000

Reexamination Certificate

active

06308308

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the design of semiconductor devices, and specifically to a method of optimizing a design layout.
BACKGROUND OF THE INVENTION
Antenna diodes are diodes that are inserted in integrated circuit layouts to protect against electrostatic discharge (ESD). ESD may be caused by accumulation of charge on a metal net connected to input gates, or inputs, during manufacturing. These gates often have thin dielectric layers which are damaged by the ESD.
The ESD through a gate dielectric occurs when there is no lower resistance path for the charge to follow. For example, when a metal net that connects to the gate also connects to a drain or source of the integrated circuit, the charge is allowed to dissipate to the diffusion area of the drain or source which provides a lower resistance path, thereby protecting the gate dielectric from the charge. Therefore, antenna diodes are connected to metal lines that otherwise during manufacturing process would be connected to a gate but not to the substrate.
The use of antenna diodes is also used with standard cell libraries. Standard cell libraries include individual standard cells implementing various logical functions. Generally, each standard cell has at least one standard cell input for receiving a signal from another standard cell or external source. These standard cells are pre-designed, and used as a “building blocks” to create a larger standard cell-based design.
At the time a standard cell is designed, it is unknown what a standard cell input will ultimately be connected to. Therefore, it cannot be determined whether an antenna will ultimately be needed because the larger design is not known. Therefore, antenna diodes are connected to each standard cell input gate to assure ESD damage does not occur during manufacturing.
Adding antenna diodes to each standard cell input has several disadvantages. The first is an increase in capacitance associated with the standard cell input. This increase in capacitance results in slower operation and increased current consumption. Second, the diode results in additional current drain. The increased current consumption results in increase power consumption. Therefore, a standard cell library that limits the number of antenna diodes would be desirable.


REFERENCES:
patent: 4989057 (1991-01-01), Lu
patent: 5212398 (1993-05-01), Matsunaga et al.
patent: 5426320 (1995-06-01), Zambrano
patent: 5500542 (1996-03-01), Iida et al.
patent: 5508548 (1996-04-01), Tailliet
patent: 5530612 (1996-06-01), Maloney
patent: 5567968 (1996-10-01), Tsuruta et al.
patent: 5594266 (1997-01-01), Beigel et al.
patent: 5637901 (1997-06-01), Beigel et al.
patent: 5763918 (1998-06-01), El-Kareh et al.
patent: 5793069 (1998-08-01), Schuelein et al.
patent: 5811857 (1998-09-01), Assaderaghi et al.
patent: 5966517 (1999-10-01), Cronin et al.
patent: 6-061440 (1994-03-01), None

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device using diode place-holders and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device using diode place-holders and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device using diode place-holders and method of... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2579236

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.