Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-11-20
2004-11-30
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S410000, C257S296000
Reexamination Certificate
active
06825538
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to semiconductor devices and, more specifically, to a process for forming an insulating layer over a semiconductor substrate that includes forming a seed layer for a high K dielectric.
BACKGROUND OF THE INVENTION
As active device dimensions get smaller, it is desirable to reduce the thickness of a gate insulating layer in such devices. The push toward thinner insulating layers is expected to limit the use of the currently popular conventional gate insulting layer, silicon dioxide. This follows because at some point of diminishing thickness, about 1 to 1.2 nm, the leakage of current through the silicon dioxide insulating layer will become unacceptably high and adversely affect device performance.
One proposed solution is to use gate insulating layers composed of a material with a higher dielectric constant than that of silicon dioxide. Such materials, termed high K dielectrics, have superior insulating characteristics compared to silicon dioxide for equivalent thicknesses, for example, by allowing less leakage current. There are, however, a number of problems with forming gate insulating layers composed of high K dielectric material. For example, it is difficult to depositing high K dielectric materials directly on hydrogen-terminated silicon substrates. To facilitate deposition, typically a template, or seed layer, of silicon dioxide is first formed between the silicon substrate and the high K dielectric material.
Alternatively, the formation of a silicon dioxide layer between the substrate and the high K dielectric may be an unavoidable by-product of the conditions and techniques used to deposit the high K dielectric or underlying seed layer on the silicon substrate. However, the formation of a silicon dioxide layer of about 1 nm or thicker defeats the purpose of switching to a high K dielectric, because the presence of the silicon dioxide layer will again give rise to the above-mentioned problems.
Previous attempts to form thin seed layers to facilitate the deposition of high K dielectrics on silicon substrates are problematic. One approach is thermal nitridation of the silicon substrate surface, to thereby form an oxidation barrier at the silicon substrate-high K dielectric interface. The temperatures used for nitridation, 550° C. and higher, however, are undesirably high for use in conjunction with conventional semiconductor processing steps of, for example, complementary metal oxide semiconductor (CMOS) or metal oxide semiconductor field effect transistor (MOSFET) fabrication. Such temperatures are undesirable because they result in an unacceptably thick seed layer (typically 0.5 to 2 nm) and further result in a high level of positive fixed charge at the semiconductor interface, both of which have deleterious effects on the device performance.
Moreover, nitridation results in the formation of an unacceptably thick nitride layer of more than about 1.5 nm. Others have attempted to incorporate nitride into the silicon substrate using ion implantation. This technique, however, still results in the formation of a silicon nitride layer that is about 0.5 to about 1.0 nm thick. Such thick nitride layers result in unacceptable amounts of positive fixed charge and charge trapping centers, both of which cause scattering of channel carriers and degradation of device performance.
Others have attempted to create a monolayer surface barrier of silicon carbide (SiC). This material is problematic, however, because the presence of carbon at the silicon surface is known to create defect states that have deleterious effects on both the leakage current and device performance. These effects may be mitigated by removing excess carbon, via for example, an oxygen anneal. An oxygen anneal, however, will cause further oxidation of the underlying silicon substrate, resulting in the formation of an undesirable silicon dioxide layer. Additionally, the carbon will itself act as a defect site, and degrade the performance of the device.
Studies of oxynitride gate dielectrics suggest that one monolayer of nitrogen atoms incorporated into a surrounding SiO
2
matrix, near a silicon channel interface, improves device performance. The techniques used for oxynitride layer formation, however, also result in the formation of undesirably thick (e.g., 0.5 to 1 nm) silicon dioxide layers at the interface. Furthermore, an oxynitride is not desirable due to its lower dielectric constant than silicon nitride (e.g., about 4.5 compared to about 7.5).
Accordingly, what is needed in the art is a semiconductor device and method of manufacturing thereof that does not exhibit the limitations of the prior art.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method of manufacturing a semiconductor device. The method includes forming an insulating layer over a silicon substrate. Forming the insulating layer includes removing hydrogen atoms from a surface of the silicon substrate to produce a substantially hydrogen-free surface. Forming the insulating layer also includes depositing a seed layer precursor over the substantially hydrogen-free surface. Forming the insulating layer further includes exposing the seed layer precursor on the surface to energized atoms to form a seed layer.
Still another embodiment is directed to an active device comprising a semiconductor substrate, an insulating layer on the semiconductor substrate, a gate electrode located over the insulating layer, and doped region located in the semiconductor substrate. The insulating layer comprises a seed layer having a thickness of about 5 Angstroms or less on the semiconductor substrate and a high K dielectric material on the seed layer.
The foregoing has outlined preferred and alternative features of the present invention so that those of ordinary skill in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the scope of the invention.
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M.L. Green, E.P. Gusev, R. Degraeve, E.L. Garfunkel; “Ultrathin(<4 nm) SiO2 and Si-O-N Gate Dielectric Layers For Silicon Microelectronics: Understanding The Processing, Structure, and Physical And Electrical Limits”; Journal of Applied Physics, vol. 90, No. 5, Sep. 1, 2001; pp. 2057-2121.
Chabal Yves
Frank Martin Michael
Wilk Glen David
Agere Systems Inc.
Lee Eddie
Owens Douglas W.
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