Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Utilizing reflow
Reexamination Certificate
1998-03-30
2001-11-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Utilizing reflow
C438S783000
Reexamination Certificate
active
06319847
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a technique for planarization of interlevel dielectric layer.
(b) Description of the Related Art
With the advance of higher integration and higher speed of semiconductor devices, each element in the device is formed of a finer pattern. The current photolithographic technique requires a higher degree of planarization or flatness of transistor elements and overlying interlevel dielectric films for achieving the finer pattern. Examples of current planarization techniques include chemical-mechanical polishing (CMP), which however raises fabrication costs of the semiconductor device and only achieves a limited profile depending on the pattern of the interlevel dielectric film to be polished.
Patent Publication JP-A-7-37879 proposes a planarization technique for a spin-on-glass (SOG) film, formed by spin-coating of silicon oxide onto a semiconductor substrate, by using a low-temperature reflow technique, after improving the quality of the SOG silicon oxide film to be equivalent to the quality of a BPSG (borophosphosilicate glass) film by using thermal oxidation of the SOG film in a steam ambient to remove impurities in the SOG film.
The proposed technique, however, involves hardening of the SOG film itself, which may impede an effective planarity thereof.
Literature “Three “Low Dt” Options for Planarizing the Pre-metal Dielectric on an Advanced Double Poly BiCMOS Process”, on Journal of Electrochemical Society, 1992, presented by W. Dauksher et al. describes a planarization technique, wherein a BPSG film comprising boron and phosphorous and formed on a transistor element is thermally treated in a steam ambient to reflow the BPSG film for planarization.
The technique of the thermal treatment of the BPSG in the steam ambient requests a temperature as high as about 800° C. in the thermal treatment for obtaining a sufficient planarity because of the high melting point of the BPSG, which temperature may affect the nature of the diffused regions formed in the preceding steps to degrade the transistor characteristics.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a new and effective planarization technique for an interlevel dielectric film in a semiconductor device.
The present invention provides a method for manufacturing a semiconductor device including the consecutive steps of forming consecutively on a semiconductor substrate a semiconductor element, a first insulating film, a second insulating film containing phosphorous and boron, and a spin-on-glass (SOG) third insulating film containing at least one of phosphorous and boron to thereby obtain a first wafer, thermal treating the first wafer in a pressurized steam ambient, thermal treating the first wafer in an inactive gas ambient, and forming an interconnect layer on the third insulating film.
In accordance with the present invention, the phosphorous or boron in the third insulating film functions for weakening the bonds in the third insulating film to facilitate the separation of the weakened bonds during the hydrolysis by the thermal treatment in the pressurized steam ambient, thereby assisting the planarization of the third insulating film. The thermal treatment in the inactive gas ambient hardens the third insulating film by removing the water content in the third insulating film incorporated during the precedent thermal oxidation.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 4420503 (1983-12-01), Leung et al.
patent: 4455325 (1984-06-01), Razouk
patent: 5409858 (1995-04-01), Thakur et al.
patent: 5679610 (1997-10-01), Matsuda et al.
patent: 5801076 (1998-09-01), Ghneim et al.
patent: 4-56221 (1992-02-01), None
patent: 6-69354 (1994-03-01), None
patent: 7-37879 (1995-02-01), None
Whitwer et al. (“Premetal Planarization Using Spin-On-Dielectric”; VMIC Conference, Jun. 12-13, 1989, pp. 96-102.*
Wolf et al. (“Silicon Processing: for the VLSI Era”; vol. 2, pp. 229-236), 1990.
Hutchins, Wheeler & Dittmar
NEC Corporation
Niebling John F.
Pompey Ron
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