Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2002-11-05
2004-04-20
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S080000, C326S062000, C326S063000, C327S333000
Reexamination Certificate
active
06724223
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device which is used in two systems having different power supply voltages.
2. Description of the Background Art
In recent years, communication information equipment have been increasingly made small in size and mobile. LSI's mounted on the equipment are required to decrease power consumption and voltage, accordingly. This is true for a DRAM which is a kind of an LSI. To meet demand for decreasing voltage, it is necessary to satisfy requirements of a 1.8 V-system interface besides a conventional TTL-system interface.
As shown in
FIG. 27
, for a TTL-system interface, an external power supply voltage VDD and an output power supply voltage VDDQ are both set at 3.3 V, VIH of an input signal is set at not less than 2.0 V and VIL of the input signal is set at not more than 0.8 V. For a 1.8 V-system interface, external power supply voltage VDD is set at 2.5 V, and output power supply voltage VDDQ is set at 1.8 V, VIH of an input signal is set at not less than 1.44 V and VIL of the input signal is set at not more than 0.36 V.
In a conventional DRAM, an internal power supply voltage VDDP (2.5 V) is generated from external power supply voltage VDD (3.3 V or 2.5 V) and an initial input inverter which uses internal power supply voltage VDDP as a driving voltage determines the logical level of an input signal.
FIG. 28
is a circuit block diagram which shows the configuration of a clock buffer
200
of the conventional DRAM. In
FIG. 28
, clock buffer
200
includes inverters
201
and
202
and a pulse generation circuit
203
which are driven by internal power supply voltage VDDP. Inverter
201
, which has a predetermined threshold voltage VTH (e.g., 1.25 V), outputs an “L” level signal if the level of a clock signal CLK is higher than that of VTH and outputs an “H” level signal if the level of clock signal CLK is lower than that of VTH. The output signal of inverter
201
is inverted by inverter
202
and the inverted signal is applied to pulse generation circuit
203
. Pulse generation circuit
203
sets a signal ZCLKF at “L” level for predetermined time in response to the rising edge of the output signal of inverter
202
. The DRAM operates synchronously with internal clock signal ZCLKF.
FIG. 29
is a circuit block diagram which shows the configuration of an input buffer
205
of the conventional DRAM. In
FIG. 29
, input buffer
205
includes inverters
206
and
207
which are driven by internal power supply voltage VDDP and a delay circuit
208
. Inverter
206
outputs an “L” level signal if the level of an address signal A
0
is higher than that of threshold voltage VTH and outputs an “H” level signal if the level of address signal A
0
is lower than that of threshold voltage VTH. The output signal of inverter
206
is inverted by inverter
207
and the inverted signal is applied to delay circuit
208
. Delay circuit
208
delays the output signal of inverter
207
by predetermined time and generates an internal address signal A
0
′. Internal address signal A
0
′ is applied to the internal circuits of the DRAM.
FIG. 30
is a circuit block diagram which shows the configuration of an input protection circuit
211
of the conventional DRAM. In
FIG. 30
, input protection circuit
211
is provided between an external pin
210
and input buffer
205
, and includes diodes
212
and
213
and a resistance element
214
. Diode
212
is connected between a node N
212
and an external power supply voltage VDD line and diode
213
is connected between a ground potential GND line and node N
212
. Node N
212
is connected to external pin
210
and also connected to an input node N
205
of input buffer
205
through resistance element
214
.
It is assumed that the threshold voltages of diodes
212
and
213
are Vth, respectively. If the potential of node N
212
is higher than VDD +Vth, diode
212
becomes conductive. If the potential of node N
212
is lower than −Vth, diode
213
becomes conductive. Therefore, even if a surge voltage is applied to external pin
210
, the potential of node N
212
is restricted to a range between −Vth and VDD +Vth, thereby protecting the internal circuits of the DRAM from the surge voltage.
FIG. 31
is a circuit diagram which shows the configuration of an output buffer
220
of the conventional DRAM. In
FIG. 31
, output buffer
220
includes P-channel MOS transistors
221
and
222
and N-channel MOS transistors
223
and
224
. MOS transistors
221
and
223
are connected in series between an output power supply potential VDDQ line and a ground potential GND line, and MOS transistors
222
and
224
are connected in series between an output power supply potential VDDQ line and a ground potential GND line. The gates of MOS transistors
221
and
223
receive an internal data signal RDH, respectively, the gate of P-channel MOS transistor
222
receives a signal ZOH which appears at a node between MOS transistors
221
and
222
, and that of N-channel MOS transistor
224
receives an internal data signal OL. An output data signal Q is outputted from a node N
222
between MOS transistors
222
and
224
.
If internal data signals RDH and OL are at “L” level and “H” level, respectively, then MOS transistors
221
and
224
become conductive, MOS transistors
222
and
223
become nonconductive and external data signal Q is set at “L” level. If internal data signals RDH and OL are “H” level and “L” level, respectively, then MOS transistors
222
and
223
become conductive, MOS transistors
221
and
224
become nonconductive and external data signal Q is set at “H” level.
The conventional DRAM has, however, the following disadvantages. In clock buffer
200
shown in
FIG. 28
, one inverter
201
which is driven by internal power supply voltage VDDP of 2.5 V determines both the level of clock signal CLK for the TTL-system interface and that of clock signal CLK for the 1.8 V-system interface. This makes it difficult to set the sizes of transistors included in inverter
201
at optimum values, respectively, which disadvantageously lowers the certainty of the determination of the level of clock signal CLK and increases a pass current which passes through inverter
201
. The pass current which passes through inverter
201
increases particularly for the 1.8 V-system interface for which the amplitude voltage of clock signal CLK is relatively smaller than power supply voltage VDDP of inverter
201
. The same thing is true for input buffer
205
shown in FIG.
29
.
Further, in a communication information equipment of a certain kind, power supply voltage VDD is set at 0 V in a standby state so as to decrease power consumption. In input protection circuit
211
shown in
FIG. 30
, if external pin
210
is applied with a “H” level voltage while power supply voltage VDD is set at 0 V, a current is carried to the power supply voltage VDD line from external pin
210
through diode
212
, which adversely influences an entire system.
Moreover, in output buffer
220
shown in
FIG. 31
, if the current driving force of P-channel MOS transistor
222
is set to be used for the TTL-system interface (VDDQ=3.3 V), it becomes insufficient for the 1.8 V-system interface (VDDQ=1.8 V). Conversely, if the current driving force of P-channel MOS transistor
222
is set to be used for the 1.8 V-system interface, it becomes excessive for the TTL-system interface.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device which can be used in two systems having different power supply voltages.
A semiconductor device according to the present invention has a first mode in which the semiconductor device is driven by a first power supply voltage and receives a first signal having an amplitude voltage lower than the first power supply voltage, and a second mode in which the semiconductor device is driven by a second power supply voltage lower than
Ichiguchi Tetsuichiro
Matsumoto Junko
Nagasawa Tsutomu
Okamoto Takeo
Suwa Makoto
McDermott & Will & Emery
Renesas Technology Corp.
Tan Vibol
LandOfFree
Semiconductor device used in two systems having different... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device used in two systems having different..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device used in two systems having different... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3244703