Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-05-30
2010-10-05
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S724000
Reexamination Certificate
active
07809997
ABSTRACT:
The present invention relates to a semiconductor device, a unique ID of the semiconductor device and a method for verifying the unique ID. Thus, original data (bit string) having 127-bit length [126:0] is inputted at step S1. Then, it is determined whether the number of bits of “1” in the bit string [126:0] inputted at the step S1is more than the half of the bits of the bit string (that is, not less than 64) or not at step S2. When the number is not less than 64, the process proceeds to step S3. At the step S3, the bit string [126:0] is inverted and an invert bit [127] is set to “1”. Then, the process proceeds to step S5. At the step S5, the fuse corresponding to the bit string [126:0] and the bit [127] are cut by LT.
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Azuma Katsuhiko
Miura Manabu
Mori Yasufumi
Buchanan & Ingersoll & Rooney PC
Ellis Kevin L
McMahon Daniel F
Renesas Electronics Corporation
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