Semiconductor device to improve data retention...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S733000, C714S763000, C714S801000, C711S106000

Reexamination Certificate

active

11078506

ABSTRACT:
A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and having the following: an ALPG receiving a start signal and a mode selection signal to generate commands and addresses with respect to a DRAM circuit with the predetermined patterns in accordance with modes, and outputting an ending signal when ending a pattern generating processing in each of modes; an ECC circuit receiving a start signal and a mode selection signal indicating a parity generation mode to generate a parity based on data read from the DRAM circuit, receiving the start signal and a mode selection signal indicating an error correction mode to perform an error correction with respect to data read from the DRAM circuit based on the parity generated in the parity generation mode and outputting data after correcting; and an interface circuit.

REFERENCES:
patent: 6381715 (2002-04-01), Bauman et al.
patent: 2002/0018389 (2002-02-01), Ito et al.
patent: 2002/0156967 (2002-10-01), Okuda
patent: 2003/0106010 (2003-06-01), Fujioka et al.
patent: 2004/0017703 (2004-01-01), Shinohara
patent: 2002-056671 (2002-02-01), None
Yamauchi et al “A Curcuit Technology for a Self- Refresh 16Mb DRAM with Less than 0.5uA/MB Data-Retention Current”, Nov. 1995, IEEE Journal of Solid-State Circuits, vol. 30, No. 11.

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