Semiconductor device that enables simultaneous read and...

Details Semiconductor device that enables simultaneous read and... Semiconductor device that enables simultaneous read and...

2005-07-19

2005-07-19

Mai, Son (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S230030, C365S185130

Reexamination Certificate

active

06920057

ABSTRACT:
A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

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Commonly assigned U.S. Appl. Nos. 09/478,057, filed Jan. 5, 2000 and 09/523,729 filed Mar. 18, 1999.

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