Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-05-12
2002-03-12
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C714S718000
Reexamination Certificate
active
06356490
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present embodiment relates to a semiconductor device in which a memory is incorporated, a testing device thereof and a testing method thereof, and, specifically, relates to a semiconductor device wherein a burn-in test is performed on a interface circuit portion to improve reliability, a testing device thereof and a testing method thereof.
2. Description of the Related Art
After a semiconductor device such as a dynamic random access memory (DRAM) is produced, a burn-in test (screening) is performed wherein the semiconductor device is heated to a high temperature and an accelerated test is performed for operations thereof.
FIG. 1
is a block diagram showing a method for an operation test by the burn-in test.
FIG. 2
is a block diagram showing a configuration of the conventional semiconductor device.
Formerly, when performing an operation test on a semiconductor device, in the order of 100 through 200 semiconductor devices to be tested
51
are connected to the semiconductor testing device
54
in parallel with each other. On a part of the terminals of the semiconductor device to be tested
51
, stress voltage is impressed at all times and the stress voltage is impressed up to a part of internal circuits of the semiconductor device to be tested
51
in accordance with the rise or fall of a scan signal. An electric current is usually supplied to a memory core portion
52
of the semiconductor device to be tested
51
by impressing stress voltage, though the stress voltage is impressed on a interface circuit portion
53
provided on the periphery, an electric current is not supplied to interior thereof. This is generally because the thickness of a silicon oxide film used for such devices as a transistor in the interface circuit portion
53
is thicker than that in the memory core
52
, malfunctions occurring first on the interface circuit portion
53
is extremely rare.
Herein, a duration of time of the operation test is, for example, in the order of 100 hours and a stress voltage in a burn-in test against a memory cell of the operating voltage of 3.3 V is, for example, in the order of 5V.
However, recently, as minute semiconductor devices are produced and are highly integrated, the silicon oxide film inside the interface circuit portion is made thin, whereby causing an increased malfunctioning frequency of the interface circuit portion. Under such circumstances, for improving reliability, it became necessary to perform a burn-in test of the interface circuit portion. However, since the interface circuit portion is readily supplied with a large electric current, there is a problem in that the power consumption increases remarkably when the stress current is supplied. Also, there is a problem wherein a testing device stops operation due to the great load on a power supply provided on a test board.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which can improve reliability while suppressing increased power consumption in the burn-in test, a testing device thereof, and testing method thereof.
According to one aspect of the present invention, a semiconductor device comprises a memory cell array, an interface circuit portion and a control circuit. The interface circuit portion controls input and output of a signal between the memory array and an external circuit. The control circuit controls operating states of the interface circuit portion independently of the memory cell array based on an externally inputted signal.
According to the invention, since the operating states of the interface circuit portion is controlled independently of the memory cell array based on the signals externally inputted, even when stress current is supplied to the interface circuit portion in the burn-in test, it is possible to control the duration of time thereof. Therefore, it becomes possible to test the interface circuit portion without consuming increased electricity, thus improving reliability.
Herein, the control circuit may include a stress control portion which controls the interface circuit portion so that stress due to an electric current is applied to the interface circuit portion in a burn-in test. In this case, it is preferable that the stress control portion controls the interface circuit portion so that the stress is applied to the interface circuit for a time period shorter than that of the stress to the memory cell array in the burn-in test.
Furthermore, the stress control portion may control the interface circuit portion so that the stress is applied to the interface circuit portion a plurality of times in the burn-in test, and may control the interface circuit portion so that the stress is applied to the interface circuit one time for a predetermined duration of time in the burn-in test.
According to another aspect of the present invention, a testing device of a semiconductor device comprises a test board on which a plurality of semiconductor devices are arranged in a lattice manner and a test circuit. Each of the semiconductor devices is provided with a memory cell array and an interface circuit portion. The interface circuit portion controls input and output of a signal between the memory cell array and an external circuit. The test circuit controls operating states of the interface circuit portion independently of the memory cell array, inputs a testing pattern signal to the semiconductor device, and detects an output signal from the semiconductor device.
According to the invention, since the operating states of the interface circuit portion is controlled independently of the memory cell array by the test circuit, even when a stress current is supplied to the interface circuit portion in the burn-in test, it is possible to control the duration of time thereof. Therefore, it becomes possible to test the interface circuit portion without consuming increased electricity, thus improving reliability.
According to another aspect of the present invention, a testing method of a semiconductor device is performing a burn-in test on a plurality of semiconductor devices. Each of the semiconductor devices is provided with a memory cell array and an interface circuit portion. The interface circuit portion controls input and output of a signal between the memory cell array and an external circuit. The burn-in test includes the steps of, controlling operating states of the interface circuit portion independently of the memory cell array, inputting a testing pattern signal to the semiconductor device, and detecting an output signal from the semiconductor device.
According to the invention, since the operating states of the interface circuit portion is controlled independently of the memory cell array, even when stress current is supplied to the interface circuit portion in the burn-in test, it is possible to control the duration of time thereof. Therefore, it becomes possible to test the whole semiconductor device without consuming increased electricity, thus improving reliability.
REFERENCES:
patent: 5535165 (1996-07-01), Davis et al.
patent: 6154860 (2000-11-01), Wright et al.
Abe Tsuneo
Matsuo Shoichi
Le Vu A.
NEC Corporation
Nguyen Van Thu
Sughrue & Mion, PLLC
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