Semiconductor device testing apparatus, system, and method...

Details Semiconductor device testing apparatus, system, and method... Semiconductor device testing apparatus, system, and method...

2007-07-31

2007-07-31

Kerveros, James C (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

10738118

ABSTRACT:
A semiconductor device testing apparatus, system, and method, in particular for testing the contacting with semiconductor devices positioned one upon the other, wherein at least two semiconductor devices are provided that are connected to a device module, at least one pin of a first semiconductor device is conductively connected with a pad, and at least one pin of a second semiconductor device also is to conductively connected with the pad. A first value is written into a memory cell of the first semiconductor device, a second value differing from the first value is written into a memory cell of the second semiconductor device, and a signal corresponding to the first value at the pin of the first semiconductor device and of a signal corresponding to the second value at the pin of the second semiconductor device is simultaneously output.

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patent: 6668347 (2003-12-01), Babella et al.
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