Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-05-19
2002-07-09
Le, N. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S600000, C324S537000, C324S1540PB
Reexamination Certificate
active
06417682
ABSTRACT:
This patent application claims priority based on Japanese patent applications, H10-308430 filed on Oct. 29, 1998, H10-137082 filed on May 19, 1998, and H10-174218 filed on Jun. 22, 1998, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus for testing a semiconductor device (also called “DUT”. For example, semiconductor integrated circuit or the like), and more particularly to a calibration jig of the semiconductor device testing apparatus and a method for calibrating the semiconductor device testing apparatus.
2. Description of Related Art
FIG. 1
is a cross sectional view of a conventional semiconductor testing apparatus. The test head
70
outputs a test signal for testing the semiconductor device
20
and receives an output signal output from the semiconductor device
20
. A performance board
66
, which transmits signals to the test head
70
through the coaxial cables
62
and
64
, is installed on the test head
70
. The coaxial cable
62
transmits the test signal from the performance board
66
to the socket board
60
. The coaxial cable
62
also transmits the output signal from the socket board
60
to the performance board
66
. A socket
50
is installed on the socket board
60
. The test signal is supplied to the semiconductor device
20
through the pin
52
and the first terminal
12
of the socket
50
. The output signal is received from the semiconductor device
20
via the second terminal
14
and the pin
54
.
The test head
70
has a driver
76
(
76
A and
76
B) for generating test signals, drive delay circuits
78
(
78
A and
78
B) for delaying the test signals generated by the drivers
76
, comparators
80
(
80
A and
80
B) for receiving the output signal, and comparator delay circuits
82
(
82
A and.
82
B) for delaying the time at which the comparators
80
output the output signal after the comparators
80
have received the output signal. The test signal output from each of the drivers
76
is measured using a measuring apparatus such as an oscilloscope. The delay times given by the driver delay circuits
78
are adjusted so that the output timings at which the test signals are output from the drivers will be equal to each other. Thus, the skews between the drivers
76
can be canceled by each other. Moreover, by adjusting the delay times given by the comparator delay circuits
82
, the skews between the comparators
80
can be canceled by each other.
FIG.
2
(
a
) is a top view of the semiconductor device
20
. FIG.
2
(
b
) is a front view of the semiconductor device
20
. The semiconductor device
20
shown here is of TSOP type. However, the semiconductor device
20
may be of QFP or BGA type. Semiconductor devices of different types can be tested by preparing a socket
50
for each of the different semiconductor device types. The semiconductor device
20
has a semiconductor device input pin
22
for inputting a signal and a semiconductor device output pin
24
for outputting a signal. These pins contact the first terminal
12
and second terminal
14
, respectively.
FIG. 3
is a cross sectional view of the socket
50
and the socket board
60
on which the socket
50
is mounted. When the socket
50
is installed on the socket board
60
along the socket guide
58
of the socket board
60
, the pins
52
and
54
of the socket
50
are inserted into the corresponding through holes
56
of the socket board
60
. Moreover, the core wires of the coaxial cables
62
and
64
are inserted into and soldered to the corresponding through holes
59
from the bottom side. In recent years, the number of pins used in the semiconductor device has increased. Hence, it is getting difficult to bring the probe of an oscilloscope or the like into contact with the first terminal
12
of the socket
50
accurately. A method for solving this problem is being proposed, in which the socket
50
is removed from the semiconductor device
20
and the probe is brought into direct contact with the socket board.
FIG. 4
is a top view of the socket board
60
. Installed on the socket board
60
are through-holes
56
for inserting the pins
52
and
54
of the socket
50
and through-holes
59
for inserting and soldering the coaxial cables
62
and
64
. Moreover, an earth pattern (GND) and a power source pattern (VDD) are installed on the top surface of the socket board
60
. By bringing the probe of the oscilloscope into contact with the socket board
60
, the semiconductor testing apparatus can be calibrated.
FIG. 5
shows a state in which the probe
44
is in contact with the socket board
60
. The probe
44
has a signal terminal
40
and an earth terminal
42
. The socket
50
is first removed from the socket board installed on the testing apparatus. The signal terminal
40
of the probe
44
is then brought into contact with the socket through-hole
56
. The earth terminal
42
is then brought into contact with the earth pattern on the socket board
60
. In this way, a signal supplied to the through-hole
56
is measured. However, when the earth pattern is not near the through-hole to be measured, the earth-line of the probe
44
connected to the earth terminal
42
must be made long. In this case, the line impedance during the measurement becomes large. In recent years, as the semiconductor device
20
becomes faster, the semiconductor device
20
needs to be tested with a higher degree of accuracy. Therefore, the semiconductor testing apparatus also needs to be calibrated with a higher degree of accuracy. However, when the line impedance is large when the test signal is measured, the semiconductor testing apparatus cannot be calibrated accurately.
The signal wire pattern and the earth pattern are installed adjacent to each other on the performance board
66
. Hence, the line impedance of the signal can be reduced by removing the socket
50
, the socket board
60
, and the coaxial cables
62
and
64
, and bringing the probe into direct contact with the performance board
66
. However in this case, the influence of the inductance and floating capacitance of the socket
50
, socket board
60
, and coaxial cables
62
and
64
do not appear on the test signal. Therefore, the semiconductor testing apparatus cannot be calibrated accurately in the actual testing state.
FIG. 6
shows another conventional method for calibrating the semiconductor testing apparatus. In this embodiment, a comparator
80
and a programmable load
180
are installed parallel with the driver
76
. By setting the programmable load
180
suitably, a load of desired level can be applied to the driver
76
. The semiconductor device
20
is removed from the socket
50
, and a test signal is output from the driver
76
. The test signal then is reflected by the top end of the socket
50
and is input to the comparator
80
. By dividing by
2
the time t
1
required for the test signal to travel from the drive
76
to the comparator
80
via the top end of the socket
50
, the signal transmission time from the drive
76
to the socket
50
can be measured.
FIG. 7
shows further another embodiment of the conventional semiconductor testing apparatus. As shown in
FIG. 7
, two coaxial cables are connected to each pin of the socket
50
. In this case, even if a test signal is generated after removing the semiconductor device
20
, the test signal is transmitted to the comparator
90
without being reflected by the socket
50
. Hence, the test signal transmission time from the drive
76
to the socket
50
cannot be measured.
FIG. 8
is a flow chart showing a conventional calibration method. First, the probe
44
is brought into contact with the through-hole
56
of the socket board
60
and the earth pattern GND, which are the points of measurement (S
302
). Next, timing measurement and calibration are carried out (S
310
). That is, the timing at which the wave form of the test signal output from a 1-channel driver rises or falls is measured to obtain calibration data. N
Hama Hiroyuki
Ishigaki Yukio
Kozuka Noriyoshi
Matsumura Shigeru
Nagai Hiroyuki
Advantest Corporation
Le N.
Rosenthal & Osha L.L.P.
Sundaram T. R.
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