Semiconductor device test structures and methods

Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21522

Reexamination Certificate

active

07858406

ABSTRACT:
Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.

REFERENCES:
patent: 5625232 (1997-04-01), Numata et al.
patent: 5625288 (1997-04-01), Snyder et al.
patent: 5675187 (1997-10-01), Numata et al.
patent: 5811352 (1998-09-01), Numata et al.
patent: 5900735 (1999-05-01), Yamamoto
patent: 6320391 (2001-11-01), Bui
patent: 6598182 (2003-07-01), Lowitz et al.
patent: 6603321 (2003-08-01), Filippi, Jr. et al.
patent: 6784000 (2004-08-01), Sikora et al.
patent: 6819124 (2004-11-01), Allee et al.
patent: 6822437 (2004-11-01), Hau-Riege et al.
patent: 6822473 (2004-11-01), Hau-Riege et al.
patent: 6919639 (2005-07-01), Ho et al.
patent: 6940720 (2005-09-01), Fischer et al.
patent: 6995392 (2006-02-01), McLaughlin et al.
patent: 7096450 (2006-08-01), Gill et al.
patent: 2003/0080761 (2003-05-01), Filippi, Jr. et al.
patent: 2005/0211980 (2005-09-01), Fischer et al.
patent: 2007/0278484 (2007-12-01), Feustel et al.
patent: 197 10 471 (1998-05-01), None
patent: 102 54 756 (2004-06-01), None
patent: 2000-223489 (2000-08-01), None
patent: 432217 (2001-05-01), None
patent: 200300055 (2003-05-01), None
Chiang, T.-Y., et al., “Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effect,” IEEE Electron Device Letters, Jan. 2002, pp. 31-33, vol. 23, No. 1, IEEE, Los Alamitos, CA.
“Electromigration,” Wikipedia, the Free Encyclopedia, http://en.wikipedia.org/wiki/Electromigration, downloaded Jan. 05, 2007, 11 pp., Wikimedia Foundation Inc., St. Petersburg, FL.
Von Glasow, A., et al., “Using the Temperature Coefficient of the Resistance (TCR) as Early Reliability Indicator for Stressvoiding Risks in Cu Interconnects,” 2003 International Reliability Physics Symposium, Apr. 1, 2003, 6 pages, IEEE, Dallas, TX.
Schindler, G., et al., “Recent Advances for Nano Interconnects: Conductor Reliability and Resistivity,” Proceedings of the Advanced Metallization Conference (AMC) 2002, 7 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device test structures and methods does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device test structures and methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device test structures and methods will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4187932

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.