Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-04-18
2003-01-07
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06504771
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a reliable memory, a system, and a method of controlling accessing to the memory.
2. Description of the Related Art
In recent years, in logic integrated circuit devices, such as ASIC (Application Specific Integrated circuits) having a semiconductor memory (e.g. a random access memory, etc.) mounted thereon, the capacity of the semiconductor memory has increased. Thus, the area occupied by the semiconductor memory has become larger, and the number of transistors has increased, within a single logic integrated circuit device.
The semiconductor memory does not satisfactorily operate, if there is even one single defective memory cell in a plurality of memory cells of the semiconductor memory. If a logic integrated circuit device includes a semiconductor memory device, having such a defective memory cell, the logic integrated circuit device is dealt as a defective circuit device. Thus, to enhance the product yield, it is required that there be a so-called “memory repairing method” of repairing the memory device having such a defective memory cell.
According to one memory repairing method, a redundant memory cell is prepared in a memory device, and a defective memory cell is replaced with the redundant memory cell. In a logic integrated circuit device having such a memory device mounted therein, there is included a redundancy circuit (a repairing circuit) for replacing the defective memory cell with a redundant cell.
The redundancy circuit operates in a manner as will be explained below. The redundancy circuit stores an address of the defective memory cell which has been detected at the testing of the wafer. If the address of this defective memory cell is specified, the redundancy circuit causes this defective memory cell not to be accessed, and causes this redundant memory cell to be accessed, instead. In this manner, if the defective memory cell is replaced with the redundant memory cell, the semiconductor integrated circuit device including the memory device can be repaired so as to normally be operated.
According to the above method, the address of the defective memory cell is stored prior to the packaging of the semiconductor integrated circuit. Therefore, if there will be a defective memory cell after the packaging, the semiconductor integrated circuit device can not be repaired.
Therefore, it is demanded that there will be a system for detecting any defective memory cell included thereinside at its usage point by itself and replacing the detected defective memory cell with a redundant memory cell, as a method of repairing the defective memory cell. Such a system is disclosed in Unexamined Japanese Patent Applicant KOKAI Publication No. H10-242288, for example.
A logic integrated circuit (LSI)
100
having the above-described structure is shown in FIG.
9
. The logic integrated circuit
100
shown in
FIG. 9
includes a logical circuit (LC)
101
and a random access memory (RAM)
102
. The random access memory
102
includes a semiconductor memory having redundant elements which are arrayed in an “X” address direction or a “Y” address direction. A built-in self-test circuit (BIST)
103
and a redundant address switching circuit (RAXC)
104
are arranged between the logical circuit
101
and the random access memory
102
. The circuits included in the logic integrated circuit
100
are connected with each other through an address bus (ADDR), a data bus (DATA) and a control-signal bus (CTL).
The built-in self-test circuit
103
performs functional testing of the random access memory
102
, at the time of power-ON resetting. The redundant address switching circuit
104
receives a result of the test from the built-in self-test circuit
103
, and automatically replaces a defective element with a redundant element.
Recently, for a memory having a large capacitance, there has been developed a constitution having a random access memory divided in a plurality of blocks. However, in the system above, if a block is deteriorated after packaging, the defective block can not be repaired. For example, in the case of a deletion in a line for enable signals or a defect of a block decoder, in which the access to the memory block is impossible. Thus, just one defective block among a plurality of blocks makes the entire memory device defective.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above. It is accordingly an object of the present invention to provide a semiconductor device including a reliable memory and a system for and method of controlling accessing to the memory.
Another object of the present invention is to provide a highly reliable semiconductor device including a plurality of memory blocks and a system for and method of controlling accessing to the memory.
In order to achieve the above object, according to the first aspect of the present invention, there is provided a semiconductor device comprising:
a memory circuit including a plurality of memory blocks and at least one redundant memory block;
a test circuit which performs functional testing of said memory circuit in unit of blocks;
a selecting-rule generating circuit which generates a selecting rule for selecting accessible memory blocks, so that the one or more memory block(s) among the plurality of the memory blocks which is(are) determined as defective by said test circuit will be avoided, while the at least one redundant memory block of the same number of the one or more memory block(s) determined as defective will be accessible;
a block selecting circuit which selects the accessible memory blocks, based on the selecting rule generated by said selecting-rule generating circuit; and
a logical circuit which accesses the accessible memory blocks to read/write data therefrom/thereto.
The test circuit may be provided in each of said memory blocks.
The test circuit may be included in said logic circuit.
The selecting-rule generating circuit may be included in said logic circuit.
The test circuit and said selecting-rule generating circuit may be included in said logic circuit.
In order to achieve the above object, according to the second aspect of the present invention, there is provided a system including the semiconductor device according to the first aspect of the present invention.
In order to achieve the above object, according to the third aspect of the present invention, there is provided a method of controlling accessing to a memory circuit comprising a plurality of memory blocks and at least one redundant memory block, said method comprising:
performing functional testing of said memory circuit in unit of the memory blocks, and determining whether each of the plurality of memory blocks is defective;
generating a selecting rule for selecting accessible memory blocks, so that the one or more memory block(s) among the plurality of the memory blocks which is(are) determined as defective by said testing will be avoided, while the at least one redundant memory block of the same number of the one or more memory block(s) determined as defective will be accessible;
selecting the accessible memory blocks, based on the selecting rule generated; and
accessing the accessible memory blocks to read/write data therefrom/thereto.
REFERENCES:
patent: 5550394 (1996-08-01), Sukegawa et al.
patent: 6144592 (2000-11-01), Kanda
patent: 6167540 (2000-12-01), Azuma
patent: 6337832 (2002-01-01), Ooishi et al.
patent: 10-242288 (1998-09-01), None
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