Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2009-02-10
2011-12-13
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S334000, C257S341000, C257SE29257
Reexamination Certificate
active
08076719
ABSTRACT:
Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery.
REFERENCES:
patent: 5168331 (1992-12-01), Yilmaz
patent: 5282018 (1994-01-01), Hiraki et al.
patent: 5525821 (1996-06-01), Harada
patent: 5637898 (1997-06-01), Baliga
patent: 5864159 (1999-01-01), Takahashi
patent: 5973359 (1999-10-01), Kobayashi
patent: 5998833 (1999-12-01), Baliga
patent: 6069372 (2000-05-01), Uenishi
patent: 6114727 (2000-09-01), Ogura et al.
patent: 6191447 (2001-02-01), Baliga
patent: 6251730 (2001-06-01), Luo
patent: 6388286 (2002-05-01), Baliga
patent: 6468878 (2002-10-01), Petruzzello et al.
patent: 6525373 (2003-02-01), Kim
patent: 6534828 (2003-03-01), Kocon
patent: 6541820 (2003-04-01), Bol
patent: 6649975 (2003-11-01), Baliga
patent: 6686244 (2004-02-01), Blanchard
patent: 6710403 (2004-03-01), Sapp
patent: 6803627 (2004-10-01), Pfirsch
patent: 2001/0001494 (2001-05-01), Kocon
patent: 2001/0041407 (2001-11-01), Brown
patent: 2003/0203576 (2003-10-01), Kitada et al.
patent: 2006/0060916 (2006-03-01), Girdhar et al.
patent: 2007/0004116 (2007-01-01), Hshieh
patent: 2007/0013000 (2007-01-01), Shiraishi
patent: 2008/0099837 (2008-05-01), Akiyama et al.
patent: 2010/0084706 (2010-04-01), Kocon
patent: 97/33320 (1997-09-01), None
patent: 2006027739 (2006-03-01), None
J. T. Watt, B. J. Fishbein & J. D. Plummer; Low-Temperature NMOS Technology with Cesium-Implanted Load Devices; IEEE Trans.Electron Devices, vol. 34, # 1, Jan. 1987; p. 28-38.
J.T.Watt,B.J.Fishbein & J.D.Plummer;Characterization of Surface Mobility in MOS Structures Containing Interfacial Cesium Ions;IEEE Trans.Electron Devices,V36,Jan. 1989; p. 96-100.
J.R.Pfiester, J.R.Alvis & C.D.Gunderson; Gain-Enhanced LDD NMOS Device Using Cesium Implantation; IEEE Trans.Electron Devices, V39, #6, Jun. 1992; p. 1469-1476.
Darwish Mohamed N.
Zeng Jun
Groover Robert
MaxPower Semiconductor Inc.
Pham Long
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