Semiconductor device, semiconductor memory device and...

Details Semiconductor device, semiconductor memory device and... Semiconductor device, semiconductor memory device and...

2001-02-22

2002-03-05

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S189050

Reexamination Certificate

active

06353565

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and, more particularly, to a test-mode setting circuit for a synchronous DRAM.
Before shipment of synchronous DRAMs (SDRAMs), a variety of tests, including a reliability test, are conducted. A test mode is entered in accordance with a command signal synchronous with an external clock signal. The test-mode entry command signals are not accessible to ordinary customers (hereinafter referred to as “users”). When a user erroneously enters a test mode, therefore, the user continues to use the SDRAM without noticing the erroneous entry. This shortens the service life of the device. It is therefore necessary to indicate to the user that such an erroneous entry has been made.
In prior art devices, when a user erroneously enters an SDRAM test mode, the column address strobe (CAS) latency is automatically altered to notify the user of the erroneous entry. Specifically, when an erroneous entry is made, the value of the CAS latency, which is “2” or “3” according to standard specifications, is changed to “1”.
More recent SDRAMs maintain the CAS latency at a value of “1”, making it impossible to change the value of the CAS latency to “1” when an erroneous entry is made. As a solution to this shortcoming, a scheme has been proposed to set the data input/output terminal of the input/output circuit of an SDRAM to a high-impedance state when an erroneous entry is made, thus disabling the data input/output operation and informing the user of the erroneous entry.
FIG. 1
is a schematic block diagram of a conventional SDRAM
50
. The SDRAM
50
sets a data input/output terminal
7
of an input/output circuit
6
to a high-impedance state when an erroneous entry is made, thus disabling the data input/output operation.
An input buffer circuit
1
receives a clock signal CLK and various control signals CKE, CS, /RAS, /CAS and /WE. The control signals are buffered and supplied to a command decoder
2
.
The command decoder
2
generates various command signals in accordance with the various control signals CKE, CS, /RAS, /CAS and /WE and sends the command signals to a peripheral circuit/memory core
3
and a plurality of test-mode decision circuits
4
.
Multiple-bit address signals A
0
-An are supplied to the peripheral circuit/memory core
3
and the test-mode decision circuits
4
via an address buffer circuit
5
.
The peripheral circuit/memory core
3
performs a data write operation or data read operation in accordance with the command signal supplied from the command decoder
2
and the address signals A
0
-An supplied from the address buffer circuit
5
.
The peripheral circuit/memory core
3
is connected to an input/output circuit
6
, which is further connected to the data input/output terminal
7
.
In data read mode, data read from the peripheral circuit/memory core
3
is sent to an external circuit via the input/output circuit
6
and the data input/output terminal
7
. In data write mode, on the other hand, write data supplied from the data input/output terminal
7
is written in memory cells (not shown) in the peripheral circuit/memory core
3
via the input/output circuit
6
.
The test-mode decision circuits
4
, each of which is provided for one of the test modes, receive the command signal from the command decoder
2
and the address signals A
0
-An. Based on the command signal and the address signals A
0
-An, the test-mode decision circuits
4
determine the test mode that is to be performed.
When detecting a test mode, each of the test-mode decision circuits
4
sends an associated one of, for example, test mode signals TEST
1
, TEST
2
, TEST
3
and TEST
4
to the peripheral circuit/memory core
3
and the test-mode output control circuit
8
. The peripheral circuit/memory core
3
operates in the test mode that corresponds to the received test mode signal.
When the test-mode output control circuit
8
determines that the received test mode signal, TEST
1
, TEST
2
, TEST
3
or TEST
4
, is a specific test mode signal that shortens the life of the device, it sends an output stop signal TESHIZ to the input/output circuit
6
.
Upon reception of the output stop signal TESHIZ, the input/output circuit
6
sets the data input/output terminal
7
to a high-impedance state.
FIG. 3
is a schematic circuit diagram of the input/output circuit
6
of the SDRAM
50
.
A node between CMOS output transistors Tr
1
and Tr
2
is connected to the data input/output terminal
7
. The output signal of an OR circuit
9
is supplied to the gate of the transistor Tr
1
, and the output signal of a NOR circuit
10
a is supplied to the gate of the transistor Tr
2
.
Read data RD is supplied to the OR circuit
9
via a data bus, and is supplied to the NOR circuit
10
a
via an inverter circuit
13
d
. The output stop signal TESHIZ is supplied to the OR circuit
9
and the NOR circuit
10
a
. A NOR circuit
10
b
is supplied with write data Din supplied to the data input/output terminal
7
and the output stop signal TESHIZ.
In the read mode, when the output stop signal TESHIZ has an L (Low) level, one of the transistors Tr
1
and Tr
2
in the input/output circuit
6
is turned on according to read data RD, causing the read data RD to be output from the data input/output terminal
7
. In the write mode, the write data Din sent to the data input/output terminal
7
is inverted by the NOR circuit
10
b and is then supplied to a write amplifier (not shown).
On the other hand, when the output stop signal TESHIZ has an H (High) level, both the transistors Tr
1
and Tr
2
are turned off so that the data input/output terminal
7
is set to a high-impedance state. This causes the output signal Din of the NOR circuit
10
b
to be fixed at an L level. The input/output circuit
6
therefore becomes inactive.
FIG. 2
is a timing chart illustrating the entry of a test mode of the SDRAM
50
.
When a mode register set command MRS is supplied as a command signal CM and a code signal Cod for setting a predetermined test mode is supplied as the address signals A
0
-An, as shown in
FIG. 2
, the test-mode decision circuits
4
determine that the mode is a test mode. The test-mode decision circuits
4
then output one of the test mode signals TEST
1
-TEST
4
.
The test-mode output control circuit
8
sends the output stop signal TESHIZ to the input/output circuit
6
so that the data input/output terminal
7
is set to a high-impedance state. As a result, read data DQ with a CAS latency of “3” is not output from the data input/output terminal
7
in accordance with, for example, a read command READ.
When a user erroneously enters a test mode of the SDRAM
50
, the data input/output operation is automatically inhibited so that the user notices the erroneous entry. This scheme can therefore prevent the device from operating in a test mode that shortens the life of the device, such as a burn-in test mode.
In the case in which a device manufacturer conducts a test on the SDRAM
50
at the time of shipment, even if the mode is set to a test mode, data input/output to or from the data input/output terminal
7
cannot be executed. The device manufacturer cannot test writing and reading data while applying the reliability test to the device.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device that can reliably detect an erroneous entry into a test mode in ordinary usage and can perform various operational tests at the time of shipment.
To achieve the above object, the present invention provides a semiconductor device including an internal circuit operated in accordance with a plurality of operation modes, including a test mode, and a test-mode control circuit connected to the internal circuit for operating the internal circuit in the test mode in accordance with a test mode command. The test-mode control circuit includes a first control circuit and a second control circuit. The first control circuit is connected to the internal circuit for inactivating at least a part of the internal circuit in accor

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