Semiconductor device, semiconductor element and method for...

Details Semiconductor device, semiconductor element and method for... Semiconductor device, semiconductor element and method for...

2000-09-26

2003-03-18

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S755000, C257S758000, C257S763000, C257S314000, C257S382000

Reexamination Certificate

active

06534867

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates generally to a device formed on a semiconductor substrate. More specifically, the invention relates to a semiconductor device having both of low-voltage and high-voltage peripheral circuits. As semiconductor devices having both of low-voltage and high-voltage peripheral circuits, there are electrically rewritable non-volatile semiconductor devices (EEPROMs), and consolidated LSIs wherein an EEPROM and another memory or a logic LSI are consolidated. The invention also relates to a semiconductor device, such as an EEPROM which has simultaneously formed cell gate and peripheral gate contact and wherein the area of the peripheral gate contact is intended to reduce. In addition, the invention relates to a semiconductor device, such as an EEPROM wherein the area of a contact in a select gate electrode is intended to reduce. Moreover, the invention relates to a method for producing the semiconductor device.
2. Related Background Art
Of semiconductor devices, electrically rewritable non-volatile semiconductor memory devices (EEPROMs) require a voltage of about 10 to 20 V in order to carry out a writing or erasing operation. In addition, an interface and logic part of such devices are driven by a voltage of, e.g., 2 to 3 V. In such devices, a circuit for handling a high voltage of 10 to 20 V, and a circuit for handling a low voltage of 2 to 3 V are consolidated on the same chip. Because high-voltage and low-voltage transistors can not generally cope with both withstand voltage and driving capacity. In addition, this is the same in the case of a chip wherein an EEPROM and a DRAM or a logic LSI are consolidated.
Each of memory cells of an EEPROM has a charge storage layer which is formed via an insulating film on the surface of a substrate, and a control gate which is formed via an insulating film. An example of a memory cell structure of an EEPROM is shown in FIG.
34
. The memory cell of
FIG. 34
is provided with a floating gate electrode FGE as a charge storage layer via an insulating film IF which is formed on the surface of a substrate SS. Moreover, a control gate electrode CGF is provided via an insulating film IF which is formed on the surface of the floating gate electrode FGE.
Data are written and erased by the entrance and exit of electrons into and from the floating gate electrode FGE, so that the threshold voltage of a transistor fluctuates.
If a voltage of 0 V is applied to a p-type well and source/drain of a selected memory cell and if a write voltage Vpp(=about 20 V) is applied to a control gate CG, a high voltage is applied between the floating gate electrode FGE and the substrate SS. Then, electrons are injected from the p-type well into a floating gate FG via an FN tunnel by a tunnel current, so that the threshold voltage moves in a positive direction.
On the other hand, if a voltage of vppe(=about 20 V) is applied to the p-type well and the source/drain and if a voltage of 0 V is applied to the control gate, electrons in the floating gate are emitted into the p-type well, so that the threshold voltage moves in a negative direction.
In the above described method, the FN tunnel current using the whole surface of a channel is utilized for the entrance and exit of electrons. As other methods, there are known a method for utilizing an FN tunnel current between the diffusion layer and gate of a transistor, and a method for utilizing the hot electron injection. In either case, a relatively high voltage (about 10 to 20 V) is necessary for write or erase.
A typical peripheral circuit for operating such an EEPROM comprises a MOS transistor. The peripheral circuit for the EEPROM is roughly divided into two kinds of transistors which include a high-voltage transistor and a low-voltage transistor.
The high-voltage transistor is used in a circuit for generating a relatively high voltage (about 10 to 20 V) necessary for write or erase and for applying the voltage to memory cells. The gate oxide film thereof has a thickness of, e.g., 40 nm, so as not to be broken at the high voltage. In order to increase a withstand voltage to a break down voltage in a p-n junction and so forth, the high-voltage transistor is designed so that the distance between a source-drain contact and an element isolating region and the distance between the contact and a gate electrode are long and so that the impurity density of a source/drain diffusion layer is low.
On the other hand, the low-voltage transistor is used in a circuit, to which no high voltage is applied. In order to increase the driving force, the thickness of the gate oxide film of the low-voltage transistor is designed to be smaller than that of the high-voltage transistor. In addition, the low-voltage transistor is designed so that the distance between a source-drain contact and an element isolating region and the distance between the contact and a gate electrode are smaller than those of the high-voltage transistor and so that that the impurity density of a source/drain diffusion layer is higher than that of the high-voltage transistor.
A conventional EEPROM comprising a memory cell array, a high-voltage transistor and a low-voltage transistor as described above is shown in plan views of FIGS.
37
(
a
) through
37
(
d
). FIGS.
38
(
a
) through
38
(
d
) and FIGS.
39
(
a
) through
39
(
d
) are sectional views taken along lines A—A′ and B—B′ of FIGS.
37
(
a
) through
37
(
d
), respectively. The peripheral circuit of this EEPROM comprises a low-voltage NMOS, a low-voltage PMOS and a high-voltage NMOS.
A conventional method for producing the semiconductor device shown in FIGS.
37
(
a
) through
37
(
d
) will be described below.
FIGS.
40
(
a
) through
46
(
d
) are plan views showing the producing method. In addition, FIGS.
47
(
a
) through
53
(
d
) and
FIGS. 54 through 60
are sectional views taken along lines A—A′ and B—B′ of FIGS.
40
(
a
) through
46
(
b
), respectively.
First, particularly as can be seen from FIG.
47
(
a
) through
47
(
d
), an element region EA defined by an element isolating region AIA is formed on a silicon substrate (a semiconductor substrate) SS. Moreover, a gate electrode GE is formed on the element region EA via a gate insulating film GIF. Then, an impurity diffusion layer, which is to be a source/drain diffusion layer, is formed to form a MOS transistor. Then, the surface of the substrate SS is covered with an interlayer insulating film IIF. Thus, the structure shown in FIGS.
40
(
a
) through
40
(
d
), FIGS.
47
(
a
) through
47
(
d
) and
FIG. 54
is obtained.
Then, as shown in FIGS.
41
(
a
) through
41
(
d
), FIGS.
48
(
l
) through
48
(
d
) and
FIG. 55
, a contact hole CH is formed in the source/drain diffusion layer DL of the memory cell part.
Subsequently, as shown in FIGS.
42
(
a
) through
42
(
d
), FIGS.
49
(
a
) through
49
(
d
) and
FIG. 56
, a polycrystalline silicon film, in which, e.g., phosphorus, is doped, is embedded in the contact hole CH.
Then, as shown in FIGS.
43
(
a
) through
43
(
d
), FIGS.
50
(
a
) through
50
(
d
) and
FIG. 57
, a contact hole CH is formed in the source/drain diffusion layer DL of each of low-voltage and high-voltage transistors.
Then, in order to decrease the contact resistance of the contact with the substrate SS, additional impurity ions are injected into the source/drain diffusion layer DL on the bottom of the contact. FIGS.
44
(
a
) through
44
(
d
), FIGS.
51
(
a
) through
51
(
d
) and
FIG. 58
show steps of injecting additional n-type ions. That is, the contact hole of the PMOS is covered with a resist PR by the photolithography, to carry out patterning so that the contact hole CH of the NMOS is exposed, and n-type impurity ions are injected.
Thereafter, the resist PR is removed, and additional p-type impurity ions pI are injected as shown in FIGS.
45
(
a
) through
45
(
d
), FIGS.
52
(
a
) through
52
(
d
) and FIG.
59
. The contact hole CH of the NMOS is covered with the resist PR, and the resist PR is patterned s

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