Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-02-22
2002-12-31
Hoang, H. (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06502225
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device, a semiconductor device design method, a recording medium recording a program for executing the semiconductor device design method, and a semiconductor device design support system and in particular to a semiconductor device, a semiconductor device design method, a semiconductor device design method recording medium, and a semiconductor device design support system capable of preventing antenna damage caused by an antenna effect occurring in a plasma step at the metal wiring formation time in a semiconductor process.
In recent semiconductor process wiring steps, various plasma techniques have been used. The representative plasma techniques include dry etching at the wiring layer patterning, plasma TEOS film deposition of wiring layer insulating film in a multi-layered wiring step, and the like, for example, which will be hereinafter referred to as plasma steps.
For example, when plasma etching is executed, if a diffusion layer does not connect to metal wiring, plasma charges accumulate in the metal wiring and an electric current flows into the gate oxide film of the transistor to which the metal wiring connects. The current causes such trouble of destruction of the gate oxide film, change in the transistor characteristics because of film quality change of the gate oxide film, or degradation of the hot carrier life. Such phenomena are called “antenna effect” and trouble caused by the antenna effect will be hereinafter referred to as “antenna damage.” This antenna damage is also caused by the antenna effect due to side walls of the of the metal wiring. In order to simplify the explanation, only areas of the metal wirings are taken into consideration.
Such antenna damage proceeds toward the worse when micro-miniaturization develops; the factors are as follows:
First, the gate oxide film itself of a transistor becomes thin and pressure resistance of the gate oxide film considerably lowers as compared with the conventional process. There is an estimation that as the film is furthermore thinned, the antenna damage is remedied because the tunnel current in the gate oxide film grows. However, it is said that antenna rule proceeds toward the worse until at least the gate oxide film thickness of about 5 nm generally used with CMOS according to 0.25-&mgr;m design rule.
Second, the minimum gate width reduces with micro-miniaturization of process, but the wiring length is not much shortened although micro-miniaturization of process develops, because the signal wiring length does not lessen if the chip size set considering yield, etc., is micro-miniaturized to about 10 mm square.
Third, although damage caused by plasma entering from a side wall of wiring at the over-etching in a dry etching step of wiring is the main factor of the antenna damage, if the wiring width is thinned, the wiring film thickness cannot be so thinned for the purposes of providing resistance to electro-migration of wiring and suppressing the resistance value.
Fourthly, as the wiring pattern becomes fine, the plasma density-at the etching time also tends to rise.
Because of the factors as described above, if the antenna ratio is about several thousands in the recent fine process, antenna damage such as destruction of a gate oxide film or characteristic degradation of a transistor has occurred during the manufacturing process in extremely general designed LSI although no problem arises even in the antenna ratio of about a hundred thousand in the conventional CMOS generation, etc., according to 0.8-&mgr;m design rule. The “antenna ratio” generally refers to the ratio between the area of a gate oxide film and the area of a conductive layer in which plasma charges occurring at the plasma etching time are accumulated.
Against the backdrop, it becomes necessary to take countermeasures against electrostatic destruction in the chip considering a wafer diffusion step apart from ESD protection on packaging and handling required for conventional I/O pins.
The above-described “antenna ratio of about several thousands” means that design considering the antenna damage is required not only for a long pattern such as a power supply, but also in general signal wiring in LSI. This is shown using general values of the current process.
For example, assuming that the area of a gate oxide film portion, namely, gate length × gate width is 0.25 &mgr;m×0.6 &mgr;m and that the wiring width is 0.4 &mgr;m and applying the antenna rule of “assuming wiring with antenna ratio=3000 or more to be an error,” the allowed wiring length becomes 1125 &mgr;m. However, in the antenna ratio calculation, the conductive layer area in which plasma charges are accumulated is calculated as the area of wiring only.
Therefore, to use such metal wiring running on one side of the chip of LSI having a chip size of 10 mm square as described above, the antenna rule is applied and the metal wiring becomes antenna wiring that can cause antenna damage. However, this does not mean that whenever such an antenna ratio is applied, antenna damage occurs. If a diffusion layer connects to the target wiring in a plasma step, plasma charges escape via the diffusion layer, thus antenna damage does not occur in the gate oxide film; this fact also need to be considered. This means that if an aluminum pattern with the gate oxide film connecting to long aluminum wiring, not connected to the diffusion layer exists, an antenna rule error occurs.
Next, how antenna damage, namely, an antenna rule error occurs in the actual LSI design and specific examples of conventional countermeasures to be taken when the antenna damage, namely, an antenna rule error occurs will be discussed.
First, specific examples of comparatively easy countermeasures against antenna image are given.
FIG. 16
is a schematic diagram to show a state in which an unused input pin in a functional block is connected to a power supply trunk and potential is fixed. In the figure, in a functional block
2101
such as-RAM or ROM, a second metal input pin
2102
unused is connected via first metal wiring
2103
to a second metal power supply trunk
104
and potential is fixed. The second metal power supply trunk
104
is connected to a third metal power supply trunk
105
. When the second metal is etched in a wiring step of such configured LSI, the third metal power supply trunk
105
does not yet exist. Thus, the second metal power supply trunk
104
becomes giant antenna wiring in a floating state not connected to a diffusion layer with respect to a gate oxide film connected to the second metal input pin
2102
unused.
Available as the countermeasures to be taken when such an antenna error occurs are a method of adding an antenna protection diode as shown in
FIG. 17A
or
17
B to the second metal power supply trunk
104
of the antenna wiring or the first metal wiring
2103
, a method of changing the first metal wiring
2103
to third metal wiring, and the like.
If an antenna protection diode is added according to the first countermeasure, plasma charges escape through a diffusion layer of the protection diode as described above, so that occurrence of antenna damage is eliminated.
FIG. 17A
is a schematic representation to show the structure of an n+ diffusion layer-P well type antenna protection diode
2201
consisting of an n+ diffusion layer
2202
and a P well
2203
fixed to power supply potential VSS and
FIG. 17B
is a schematic representation to show the structure of a p+ diffusion layer-N well type antenna protection diode
2211
consisting of a p+ diffusion layer
2212
and an N well
2213
fixed to power supply potential VDD.
If the first metal wiring
2103
is changed to third metal wiring according to the second countermeasure, the functional block
2101
and the second metal power supply trunk
104
are separated at the etching time of the second metal forming the second metal power supply trunk
104
, thus antenna damage cannot occur.
If an unused input pin is fixed in a normal block formed of a
Hoang H.
Matsushita Electric - Industrial Co., Ltd.
Pearne & Gordon LLP
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