Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-08
2007-05-08
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10960720
ABSTRACT:
A routing method of a semiconductor device includes steps (a) to (c). The step (a) checks a relation between a first interconnection pattern to be routed and a second interconnection pattern to be routed, wherein a line width of the second interconnection pattern is thicker than that of the first interconnection pattern. The step (b) refers to a routing rule of a design rule corresponding to a connection between the first interconnection pattern and the second interconnection pattern, when the first interconnection pattern and the second interconnection pattern would be routed in a same layer and connected each other. The step (c) routes the first interconnection pattern and the second interconnection such that the first interconnection is not bent in an area defined based on the routing rule.
REFERENCES:
patent: 6505333 (2003-01-01), Tanaka
patent: 6539530 (2003-03-01), Torii
patent: 6732345 (2004-05-01), Kato
patent: 6957411 (2005-10-01), Teig et al.
patent: 7065729 (2006-06-01), Chapman
patent: 3390393 (2003-03-01), None
Dinh Paul
Foley & Lardner LLP
NEC Electronics Corporation
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