Semiconductor device realized by using partial SOI technology

Details Semiconductor device realized by using partial SOI technology Semiconductor device realized by using partial SOI technology

2002-04-05

2003-03-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S051000

Reexamination Certificate

active

06529399

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-401302, filed Dec. 28, 2001; and No. 2002-051882, filed Feb. 27, 2002, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device realized typically by using SOI (silicon on insulator) or SON (silicon on nothing) technology.
2. Description of the Related Art
Efforts have been paid in recent years to utilize SOI technology for manufacturing semiconductor devices in order to realize a high speed operation for electronic devices. MOS transistors formed on the surface of an SOI substrate (to be referred to as an SOI element hereinafter) show characteristic features including a large high current drivability, a small junction capacity and non-existence of back gate effect. Thus, a high speed circuit operation can be realized by utilizing these characteristic features.
However, particularly, a PD-SOI element that operates in a state of partial depletion shows such a hysteres is that the static characteristics of the transistor can vary depending on the immediately preceding operating condition thereof. Therefore, when a transfer gate of a memory cell is formed by using an SOI element, its cutoff performance is degraded to in turn degrade the data holding performance of the memory cell. Additionally, paired SOI elements can hardly operate properly. Thus, it is very difficult to form complementary latch circuits and operational amplifiers by using an SOI element.
Meanwhile, the merged DRAM technology of merging logic circuits and DRAMs on a single chip has been attracting attention in recent years. Using this technology, it is possible to arrange large capacity memory devices and logic circuits on the same chip. Additionally, the merged DRAM technology makes it possible to connect an arithmetic and logic unit and a memory device by means of a data path having a large bus width, in order to realize a high speed operation. However, a DRAM is normally made to comprise a large number of transfer gates and complementary circuits and, as pointed out above, it is difficult to form transfer gates and complementary circuits by using SOI elements. Thus, it has been believed that it is difficult to manufacture DRAMs by using SOI technology.
Recently, there has been proposed a technique of forming a DRAM by producing a bulk region in part of an SOI wafer. This technique is referred to as partial SOI. More specifically, it is a semiconductor manufacturing technique of forming an opening in part of an SOI wafer and subsequently closing the opening by growing monocrystalline silicon in the opening to produce a bulk region there. When using this technique, it is necessary to provide a buffer region of several micrometers along the border of the SOI region and the bulk region. Additionally, the bulk regions of a chip are required to be uniformized in terms of shape and size in order to grow good quality monocrystalline silicon.
It may be easy to design and manufacture a merged DRAM chip having logic circuits by using the partial SOI technique and forming the entire DRAM macro as a large bulk region. However, such a design concept by turn gives rise to the problems as pointed out below. Firstly, with such a design concept, it is not possible to exploit the advantages of an SOI element in order to improve the performance of the DRAM macro itself.
Secondly, the capacity and the configuration of the DRAM macro are restricted when the bulk regions are uniformized in terms of shape and size. A highly integrated high performance semiconductor device that is referred to as “system on chip type” is formed by putting a large number of versatile functional blocks together. Each functional block is required to have a memory macro showing an optimal capacity and an optimal configuration and designed to operate optimally. Recently, merged DRAM macros whose memory capacity ranges between 1 Mbit and 128 Mbits are commercially available to meet the requirement. Additionally, available data bus width ranges between 64 bits and 256 bits and hence it is possible to select an appropriate data bus width depending on the application. Furthermore, DRAM macros having parity bits as many as 144 bits are also available. High speed DRAMs having an access time as short as 5 ns have been proposed recently. The area and the shape of a DRAM macro can vary depending on its capacity and the configuration. They can also vary depending on its operating speed. This means that bulk regions with different shapes and areas need to be provided. However, providing bulk regions with different shapes and areas is a costly operation because the manufacturing process needs to be optimized for each shape and each area of bulk region. Therefore, it may not be wise to form bulk regions having different areas and shapes on the same chip. Manufacturing chips, each having bulk regions with different shapes and areas, can end up with an extremely low yield. The subject was described about the partial SOI technique. However, the partial SON has the same subject as the partial SOI technique. Thus, there is a demand for semiconductor devices manufactured by using the partial SOI or SON technique and comprising circuits that show desired operating characteristics.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a semiconductor device comprising: a bulk region formed in a semiconductor substrate; and a semiconductor region formed on one of a buried insulating film in the semiconductor substrate and a cavity region formed in the semiconductor substrate; the bulk region including: a memory cell array having a plurality of memory cells arranged in the form of a matrix and including a plurality of memory cells connected to bit lines and word lines; sense amplifier connected to the bit lines of the memory cell array, the sense amplifier being adapted to sense and amplify the potentials of the bit lines; and column selection gate for connecting the sense amplifier to first data line; the semiconductor region including: word line selection circuit for selecting appropriate ones of the word lines; and column selection circuit for selecting appropriate ones of the column selection gate.
According to another aspect of the invention, there is provided a semiconductor device formed in a region other than the bulk region within a semiconductor substrate, the device comprising: a delay circuit adapted to be supplied with a clock signal and delay the clock signal; a logic circuit adapted to be supplied with the output signal of the delay circuit and the clock signal; the delay circuit including: an inverter circuit for receiving the clock signal; a capacitor to be charged and discharged in response to the operation of the inverter circuit; and a transistor connected to the capacitor and the output terminal of the inverter circuit, the transistor being turned off in response to a fall of the output voltage of the inverter circuit under the threshold voltage of the inverter circuit.


REFERENCES:
patent: 5740099 (1998-04-01), Tanigawa
patent: 6483749 (2002-11-01), Choi et al.
Paul DeMone, et al., “A 6.25 ns Random Access 0.25 &mgr;m Embedded DRAM”, 2001 Symposium on VLSI Circuits Digest of Technical Papers, 4-89114-013-5.

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